Commit ec775d0e authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

powerpc: Convert to new irq_* function names



Scripted with coccinelle.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 7bfbc1f2
......@@ -830,7 +830,7 @@ unsigned int irq_create_of_mapping(struct device_node *controller,
/* Set type if specified and different than the current one */
if (type != IRQ_TYPE_NONE &&
type != (irqd_get_trigger_type(irq_get_irq_data(virq))))
set_irq_type(virq, type);
irq_set_irq_type(virq, type);
return virq;
}
EXPORT_SYMBOL_GPL(irq_create_of_mapping);
......@@ -853,7 +853,7 @@ void irq_dispose_mapping(unsigned int virq)
return;
/* remove chip and handler */
set_irq_chip_and_handler(virq, NULL, NULL);
irq_set_chip_and_handler(virq, NULL, NULL);
/* Make sure it's completed */
synchronize_irq(virq);
......@@ -1158,7 +1158,7 @@ static int virq_debug_show(struct seq_file *m, void *private)
seq_printf(m, "%5d ", i);
seq_printf(m, "0x%05lx ", virq_to_hw(i));
chip = get_irq_desc_chip(desc);
chip = irq_desc_get_chip(desc);
if (chip && chip->name)
p = chip->name;
else
......
......@@ -31,7 +31,7 @@ void machine_kexec_mask_interrupts(void) {
if (!desc)
continue;
chip = get_irq_desc_chip(desc);
chip = irq_desc_get_chip(desc);
if (!chip)
continue;
......
......@@ -261,7 +261,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
virq = irq_create_mapping(NULL, line);
if (virq != NO_IRQ)
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
} else {
pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
oirq.size, oirq.specifier[0], oirq.specifier[1],
......
......@@ -133,7 +133,7 @@ cpld_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq);
return 0;
}
......@@ -198,7 +198,7 @@ mpc5121_ads_cpld_pic_init(void)
goto end;
}
set_irq_chained_handler(cascade_irq, cpld_pic_cascade);
irq_set_chained_handler(cascade_irq, cpld_pic_cascade);
end:
of_node_put(np);
}
......@@ -82,7 +82,7 @@ static struct irq_chip media5200_irq_chip = {
void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int sub_virq, val;
u32 status, enable;
......@@ -116,8 +116,8 @@ static int media5200_irq_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
set_irq_chip_data(virq, &media5200_irq);
set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
irq_set_chip_data(virq, &media5200_irq);
irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
irq_set_status_flags(virq, IRQ_LEVEL);
return 0;
}
......@@ -182,8 +182,8 @@ static void __init media5200_init_irq(void)
media5200_irq.irqhost->host_data = &media5200_irq;
set_irq_data(cascade_virq, &media5200_irq);
set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
irq_set_handler_data(cascade_virq, &media5200_irq);
irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
return;
......
......@@ -192,7 +192,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq);
int sub_virq;
u32 status;
......@@ -209,8 +209,8 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
struct mpc52xx_gpt_priv *gpt = h->host_data;
dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
set_irq_chip_data(virq, gpt);
set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
irq_set_chip_data(virq, gpt);
irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
return 0;
}
......@@ -259,8 +259,8 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
}
gpt->irqhost->host_data = gpt;
set_irq_data(cascade_virq, gpt);
set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
irq_set_handler_data(cascade_virq, gpt);
irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
/* If the GPT is currently disabled, then change it to be in Input
* Capture mode. If the mode is non-zero, then the pin could be
......
......@@ -214,7 +214,7 @@ static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
ctrl_reg |= (type << (22 - (l2irq * 2)));
out_be32(&intr->ctrl, ctrl_reg);
__set_irq_handler_unlocked(d->irq, handler);
__irq_set_handler_locked(d->irq, handler);
return 0;
}
......@@ -414,7 +414,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
else
hndlr = handle_level_irq;
set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
__func__, l2irq, virq, (int)irq, type);
return 0;
......@@ -431,7 +431,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
return -EINVAL;
}
set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
return 0;
......
......@@ -81,7 +81,7 @@ static struct irq_chip pq2ads_pci_ic = {
static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
{
struct pq2ads_pci_pic *priv = get_irq_desc_data(desc);
struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
u32 stat, mask, pend;
int bit;
......@@ -107,16 +107,16 @@ static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_data(virq, h->host_data);
set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
irq_set_chip_data(virq, h->host_data);
irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
return 0;
}
static void pci_host_unmap(struct irq_host *h, unsigned int virq)
{
/* remove chip and handler */
set_irq_chip_data(virq, NULL);
set_irq_chip(virq, NULL);
irq_set_chip_data(virq, NULL);
irq_set_chip(virq, NULL);
}
static struct irq_host_ops pci_pic_host_ops = {
......@@ -175,8 +175,8 @@ int __init pq2ads_pci_init_irq(void)
priv->host = host;
host->host_data = priv;
set_irq_data(irq, priv);
set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
irq_set_handler_data(irq, priv);
irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
of_node_put(np);
return 0;
......
......@@ -56,7 +56,7 @@ static void machine_restart(char *cmd)
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
......@@ -106,7 +106,7 @@ static void __init ksi8560_pic_init(void)
cpm2_pic_init(np);
of_node_put(np);
set_irq_chained_handler(irq, cpm2_cascade);
irq_set_chained_handler(irq, cpm2_cascade);
#endif
}
......
......@@ -50,7 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
......@@ -101,7 +101,7 @@ static void __init mpc85xx_ads_pic_init(void)
cpm2_pic_init(np);
of_node_put(np);
set_irq_chained_handler(irq, cpm2_cascade);
irq_set_chained_handler(irq, cpm2_cascade);
#endif
}
......
......@@ -255,7 +255,7 @@ static int mpc85xx_cds_8259_attach(void)
}
/* Success. Connect our low-level cascade handler. */
set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
return 0;
}
......
......@@ -47,7 +47,7 @@
#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ) {
......@@ -122,7 +122,7 @@ void __init mpc85xx_ds_pic_init(void)
i8259_init(cascade_node, 0);
of_node_put(cascade_node);
set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
#endif /* CONFIG_PPC_I8259 */
}
......
......@@ -41,7 +41,7 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
......@@ -92,7 +92,7 @@ static void __init sbc8560_pic_init(void)
cpm2_pic_init(np);
of_node_put(np);
set_irq_chained_handler(irq, cpm2_cascade);
irq_set_chained_handler(irq, cpm2_cascade);
#endif
}
......
......@@ -93,7 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq)
void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq;
/*
......@@ -246,8 +246,8 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
{
/* All interrupts are LEVEL sensitive */
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
handle_fasteoi_irq);
irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip,
handle_fasteoi_irq);
return 0;
}
......@@ -308,8 +308,8 @@ void socrates_fpga_pic_init(struct device_node *pic)
pr_warning("FPGA PIC: can't get irq%d.\n", i);
continue;
}
set_irq_chained_handler(socrates_fpga_irqs[i],
socrates_fpga_pic_cascade);
irq_set_chained_handler(socrates_fpga_irqs[i],
socrates_fpga_pic_cascade);
}
socrates_fpga_pic_iobase = of_iomap(pic, 0);
......
......@@ -46,7 +46,7 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
......@@ -102,7 +102,7 @@ static void __init stx_gp3_pic_init(void)
cpm2_pic_init(np);
of_node_put(np);
set_irq_chained_handler(irq, cpm2_cascade);
irq_set_chained_handler(irq, cpm2_cascade);
#endif
}
......
......@@ -44,7 +44,7 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
......@@ -100,7 +100,7 @@ static void __init tqm85xx_pic_init(void)
cpm2_pic_init(np);
of_node_put(np);
set_irq_chained_handler(irq, cpm2_cascade);
irq_set_chained_handler(irq, cpm2_cascade);
#endif
}
......
......@@ -95,7 +95,7 @@ static int gef_pic_cascade_irq;
void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq;
/*
......@@ -164,7 +164,7 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
{
/* All interrupts are LEVEL sensitive */
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
return 0;
}
......@@ -225,7 +225,7 @@ void __init gef_pic_init(struct device_node *np)
return;
/* Chain with parent controller */
set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
}
/*
......
......@@ -19,7 +19,7 @@
#ifdef CONFIG_PPC_I8259
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
......@@ -77,6 +77,6 @@ void __init mpc86xx_init_irq(void)
i8259_init(cascade_node, 0);
of_node_put(cascade_node);
set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade);
#endif
}
......@@ -226,11 +226,11 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(cascade_irq);
chip = get_irq_desc_chip(cdesc);
chip = irq_desc_get_chip(cdesc);
chip->irq_eoi(&cdesc->irq_data);
}
chip = get_irq_desc_chip(desc);
chip = irq_desc_get_chip(desc);
chip->irq_eoi(&desc->irq_data);
}
......@@ -251,5 +251,5 @@ void __init mpc8xx_pics_init(void)
irq = cpm_pic_init();
if (irq != NO_IRQ)
set_irq_chained_handler(irq, cpm_cascade);
irq_set_chained_handler(irq, cpm_cascade);
}
......@@ -93,8 +93,8 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_desc_chip(desc);
struct axon_msic *msic = get_irq_data(irq);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct axon_msic *msic = irq_get_handler_data(irq);
u32 write_offset, msi;
int idx;
int retry = 0;
......@@ -287,7 +287,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
}
dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
set_irq_msi(virq, entry);
irq_set_msi_desc(virq, entry);
msg.data = virq;
write_msi_msg(virq, &msg);
}
......@@ -305,7 +305,7 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
if (entry->irq == NO_IRQ)
continue;
set_irq_msi(entry->irq, NULL);
irq_set_msi_desc(entry->irq, NULL);
irq_dispose_mapping(entry->irq);
}
}
......@@ -320,7 +320,7 @@ static struct irq_chip msic_irq_chip = {
static int msic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
return 0;
}
......@@ -400,8 +400,8 @@ static int axon_msi_probe(struct platform_device *device)
msic->irq_host->host_data = msic;
set_irq_data(virq, msic);
set_irq_chained_handler(virq, axon_msi_cascade);
irq_set_handler_data(virq, msic);
irq_set_chained_handler(virq, axon_msi_cascade);
pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
/* Enable the MSIC hardware */
......
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