- 24 Sep, 2010 12 commits
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Ben Skeggs authored
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Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Will be used at a later point when we plug in an alternative VRAM memory manager for GeForce 8+ boards. Based on pscnv code to do the same. Signed-off-by:
Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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- 26 Aug, 2010 1 commit
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Francisco Jerez authored
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- 17 Aug, 2010 1 commit
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Ben Skeggs authored
When VRAM is running out it's possible that the client's push buffers get evicted to main memory. When they're validated back in, the GPU may be used for the copy back to VRAM, but the existing synchronisation code only deals with inter-channel sync, not sync between PFIFO and PGRAPH on the same channel. This leads to PFIFO fetching from command buffers that haven't quite been copied by PGRAPH yet. This patch marks push buffers as so, and forces any GPU-assisted buffer moves to be done on a different channel, which triggers the correct synchronisation to happen before we submit them. Signed-off-by:
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- 05 Aug, 2010 3 commits
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Ben Skeggs authored
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Francisco Jerez authored
sil164 and friends are the most common, usually they just need to be poked once because a fixed configuration is enough for any modes and clocks, so they worked without this patch if the BIOS had done a good job on POST. Display couldn't survive a suspend/resume cycle though. Unfortunately, BIOS scripts are useless here. Signed-off-by:
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Ben Skeggs authored
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- 03 Aug, 2010 1 commit
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Dave Airlie authored
I wrote this for the prime sharing work, but I also noticed other external non-upstream drivers from a large company carrying a similiar patch, so I may as well ship it in master. Signed-off-by:Dave Airlie <airlied@redhat.com>
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- 26 Jul, 2010 9 commits
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Ben Skeggs authored
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Francisco Jerez authored
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Francisco Jerez authored
BIOS scripts usually make an attempt to reset the AGP controller, however on some nv4x cards doing it properly involves switching FW off and on: if we do that without updating the AGP bridge settings accordingly (e.g. with the corresponding calls to agp_enable()) we will be locking ourselves out of the card MMIO space. Do it from nouveau_mem_reset_agp() before the init scripts are executed. Signed-off-by:
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Francisco Jerez authored
Fixes the randomly flashing vertical lines seen on some nv3x after a cold-boot. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Based on a patch from Matthew Garrett. Signed-off-by:
Matthew Garrett <mjg@redhat.com>
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Ben Skeggs authored
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- 13 Jul, 2010 12 commits
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This was always really a developer option, and if it's really necessary we can hack this in ourselves. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: -
Ben Skeggs authored
Nouveau will no longer load at all if card initialisation fails, so all these checks are unnecessary. Signed-off-by: -
Ben Skeggs authored
The previous handler basically worked correctly for a full-blown mode change. However, it did nothing at all when a partial (encoder only) reconfiguation was necessary, leading to the display hanging on certain types of mode switch. Signed-off-by: -
Francisco Jerez authored
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Ben Skeggs authored
Create connectors before encoders to avoid having to do another loop across encoder list whenever we create a new connector. This allows us to pass the connector to the encoder creation functions, and avoid using a create_resources() callback since we can now call it directly. This can also potentially modify the connector ordering on nv50. On cards where the DCB connector and encoder tables are in the same order, things will be unchanged. However, there's some cards where the ordering between the tables differ, and in one case, leads us to naming the connectors "wrongly". Signed-off-by: -
Ben Skeggs authored
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- 01 Jun, 2010 1 commit
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Dave Airlie authored
Some of the laptops with the switchable graphics, seem to not post the secondary GPU at all, and we can't find a copy of the BIOS anywhere except in the ACPI rom retrieval. This adds support for ACPI ROM retrieval to nouveau. Signed-off-by:
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