1. 06 Nov, 2013 2 commits
    • Gavin Shan's avatar
      powerpc/powernv: Reserve the correct PE number · 36954dc7
      Gavin Shan authored
      
      
      We're assigning PE numbers after the completion of PCI probe. During
      the PCI probe, we had PE#0 as the super container to encompass all
      PCI devices. However, that's inappropriate since PELTM has ascending
      order of priority on search on P7IOC. So we need PE#127 takes the
      role that PE#0 has previously. For PHB3, we still have PE#0 as the
      reserved PE.
      
      The patch supposes that the underly firmware has built the RID to
      PE# mapping after resetting IODA tables: all PELTM entries except
      last one has invalid mapping on P7IOC, but all RTEs have binding
      to PE#0. The reserved PE# is being exported by firmware by device
      tree.
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      36954dc7
    • Gavin Shan's avatar
      powerpc/powernv: Add PE to its own PELTV · 631ad691
      Gavin Shan authored
      
      
      We need add PE to its own PELTV. Otherwise, the errors originated
      from the PE might contribute to other PEs. In the result, we can't
      clear up the error successfully even we're checking and clearing
      errors during access to PCI config space.
      
      Cc: stable@vger.kernel.org
      Reported-by: kalshett@in.ibm.com
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      631ad691
  2. 11 Oct, 2013 4 commits
  3. 14 Aug, 2013 4 commits
  4. 24 Jul, 2013 1 commit
  5. 01 Jul, 2013 2 commits
  6. 21 Jun, 2013 1 commit
  7. 20 Jun, 2013 2 commits
    • Gavin Shan's avatar
      powerpc/eeh: Initialization for PowerNV · e9cc17d4
      Gavin Shan authored
      
      
      The patch initializes EEH for PowerNV platform. Because the OPAL
      APIs requires HUB ID, we need trace that through struct pnv_phb.
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e9cc17d4
    • Alexey Kardashevskiy's avatar
      powerpc/vfio: Enable on PowerNV platform · 4e13c1ac
      Alexey Kardashevskiy authored
      
      
      This initializes IOMMU groups based on the IOMMU configuration
      discovered during the PCI scan on POWERNV (POWER non virtualized)
      platform.  The IOMMU groups are to be used later by the VFIO driver,
      which is used for PCI pass through.
      
      It also implements an API for mapping/unmapping pages for
      guest PCI drivers and providing DMA window properties.
      This API is going to be used later by QEMU-VFIO to handle
      h_put_tce hypercalls from the KVM guest.
      
      The iommu_put_tce_user_mode() does only a single page mapping
      as an API for adding many mappings at once is going to be
      added later.
      
      Although this driver has been tested only on the POWERNV
      platform, it should work on any platform which supports
      TCE tables.  As h_put_tce hypercall is received by the host
      kernel and processed by the QEMU (what involves calling
      the host kernel again), performance is not the best -
      circa 220MB/s on 10Gb ethernet network.
      
      To enable VFIO on POWER, enable SPAPR_TCE_IOMMU config
      option and configure VFIO as required.
      
      Cc: David Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      4e13c1ac
  8. 24 May, 2013 1 commit
  9. 10 May, 2013 1 commit
  10. 06 May, 2013 1 commit
    • Benjamin Herrenschmidt's avatar
      powerpc/pci: Support per-aperture memory offset · 3fd47f06
      Benjamin Herrenschmidt authored
      
      
      The PCI core supports an offset per aperture nowadays but our arch
      code still has a single offset per host bridge representing the
      difference betwen CPU memory addresses and PCI MMIO addresses.
      
      This is a problem as new machines and hypervisor versions are
      coming out where the 64-bit windows will have a different offset
      (basically mapped 1:1) from the 32-bit windows.
      
      This fixes it by using separate offsets. In the long run, we probably
      want to get rid of that intermediary struct pci_controller and have
      those directly stored into the pci_host_bridge as they are parsed
      but this will be a more invasive change.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3fd47f06
  11. 05 May, 2013 1 commit
  12. 26 Apr, 2013 5 commits
  13. 18 Apr, 2013 1 commit
  14. 03 Jan, 2013 1 commit
    • Greg Kroah-Hartman's avatar
      POWERPC: drivers: remove __dev* attributes. · cad5cef6
      Greg Kroah-Hartman authored
      
      
      CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
      markings need to be removed.
      
      This change removes the use of __devinit, __devexit_p, __devinitdata,
      __devinitconst, and __devexit from these drivers.
      
      Based on patches originally written by Bill Pemberton, but redone by me
      in order to handle some of the coding style issues better, by hand.
      
      Cc: Bill Pemberton <wfp5p@virginia.edu>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      cad5cef6
  15. 15 Nov, 2012 1 commit
  16. 17 Sep, 2012 8 commits
  17. 11 Sep, 2012 1 commit
    • Gavin Shan's avatar
      powerpc/powernv: I/O and memory alignment for P2P bridges · 271fd03a
      Gavin Shan authored
      
      
      The patch implements ppc_md.pcibios_window_alignment for powernv
      platform so that the resource reassignment in PCI core will be
      done according to the I/O and memory alignment returned from
      powernv platform. The alignments returned from powernv platform
      is closely depending on the scheme for PE segmenting. Besides,
      the patch isn't useful for now, but the subsequent patches will
      be working based on it.
      
      [bhelgaas: use pci_pcie_type() since pci_dev.pcie_type was removed]
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      271fd03a
  18. 05 Sep, 2012 1 commit
  19. 23 Aug, 2012 1 commit
  20. 13 Jun, 2012 1 commit