1. 06 Nov, 2013 1 commit
    • Gavin Shan's avatar
      powerpc/powernv: Reserve the correct PE number · 36954dc7
      Gavin Shan authored
      
      
      We're assigning PE numbers after the completion of PCI probe. During
      the PCI probe, we had PE#0 as the super container to encompass all
      PCI devices. However, that's inappropriate since PELTM has ascending
      order of priority on search on P7IOC. So we need PE#127 takes the
      role that PE#0 has previously. For PHB3, we still have PE#0 as the
      reserved PE.
      
      The patch supposes that the underly firmware has built the RID to
      PE# mapping after resetting IODA tables: all PELTM entries except
      last one has invalid mapping on P7IOC, but all RTEs have binding
      to PE#0. The reserved PE# is being exported by firmware by device
      tree.
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      36954dc7
  2. 11 Oct, 2013 3 commits
  3. 01 Jul, 2013 2 commits
  4. 21 Jun, 2013 1 commit
  5. 20 Jun, 2013 2 commits
  6. 10 May, 2013 1 commit
  7. 26 Apr, 2013 3 commits
  8. 18 Apr, 2013 1 commit
  9. 17 Sep, 2012 2 commits
  10. 07 Dec, 2011 1 commit
  11. 25 Nov, 2011 1 commit
    • Benjamin Herrenschmidt's avatar
      powerpc/powernv: PCI support for p7IOC under OPAL v2 · 184cd4a3
      Benjamin Herrenschmidt authored
      
      
      This adds support for p7IOC (and possibly other IODA v1 IO Hubs)
      using OPAL v2 interfaces.
      
      We completely take over resource assignment and assign them using an
      algorithm that hands out device BARs in a way that makes them fit in
      individual segments of the M32 window of the bridge, which enables us
      to assign individual PEs to devices and functions.
      
      The current implementation gives out a PE per functions on PCIe, and a
      PE for the entire bridge for PCIe to PCI-X bridges.
      
      This can be adjusted / fine tuned later.
      
      We also setup DMA resources (32-bit only for now) and MSIs (both 32-bit
      and 64-bit MSI are supported).
      
      The DMA allocation tries to divide the available 256M segments of the
      32-bit DMA address space "fairly" among PEs. This is done using a
      "weight" heuristic which assigns less value to things like OHCI USB
      controllers than, for example SCSI RAID controllers. This algorithm
      will probably want some fine tuning for specific devices or device
      types.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      184cd4a3
  12. 20 Sep, 2011 2 commits