1. 08 Jun, 2009 4 commits
  2. 05 Jun, 2009 1 commit
  3. 04 Jun, 2009 2 commits
  4. 02 Jun, 2009 1 commit
  5. 30 May, 2009 1 commit
  6. 29 May, 2009 4 commits
    • David S. Miller's avatar
      sparc64: Fix section attribute warnings. · 6373fffc
      David S. Miller authored
      
      
      CSUM copy to/from user assembler was missing allocatable and
      executable attributes for .fixup
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6373fffc
    • Mel Gorman's avatar
      x86: ignore VM_LOCKED when determining if hugetlb-backed page tables can be shared or not · 32b154c0
      Mel Gorman authored
      Addresses http://bugzilla.kernel.org/show_bug.cgi?id=13302
      
      
      
      On x86 and x86-64, it is possible that page tables are shared beween
      shared mappings backed by hugetlbfs.  As part of this,
      page_table_shareable() checks a pair of vma->vm_flags and they must match
      if they are to be shared.  All VMA flags are taken into account, including
      VM_LOCKED.
      
      The problem is that VM_LOCKED is cleared on fork().  When a process with a
      shared memory segment forks() to exec() a helper, there will be shared
      VMAs with different flags.  The impact is that the shared segment is
      sometimes considered shareable and other times not, depending on what
      process is checking.
      
      What happens is that the segment page tables are being shared but the
      count is inaccurate depending on the ordering of events.  As the page
      tables are freed with put_page(), bad pmd's are found when some of the
      children exit.  The hugepage counters also get corrupted and the Total and
      Free count will no longer match even when all the hugepage-backed regions
      are freed.  This requires a reboot of the machine to "fix".
      
      This patch addresses the problem by comparing all flags except VM_LOCKED
      when deciding if pagetables should be shared or not for hugetlbfs-backed
      mapping.
      Signed-off-by: default avatarMel Gorman <mel@csn.ul.ie>
      Acked-by: default avatarHugh Dickins <hugh.dickins@tiscali.co.uk>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: <stable@kernel.org>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
      Cc: <starlight@binnacle.cx>
      Cc: Eric B Munson <ebmunson@us.ibm.com>
      Cc: Adam Litke <agl@us.ibm.com>
      Cc: Andy Whitcroft <apw@canonical.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      32b154c0
    • Oskar Schirmer's avatar
      flat: fix data sections alignment · c3dc5bec
      Oskar Schirmer authored
      
      
      The flat loader uses an architecture's flat_stack_align() to align the
      stack but assumes word-alignment is enough for the data sections.
      
      However, on the Xtensa S6000 we have registers up to 128bit width
      which can be used from userspace and therefor need userspace stack and
      data-section alignment of at least this size.
      
      This patch drops flat_stack_align() and uses the same alignment that
      is required for slab caches, ARCH_SLAB_MINALIGN, or wordsize if it's
      not defined by the architecture.
      
      It also fixes m32r which was obviously kaput, aligning an
      uninitialized stack entry instead of the stack pointer.
      
      [akpm@linux-foundation.org: coding-style fixes]
      Signed-off-by: default avatarOskar Schirmer <os@emlix.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Cc: Bryan Wu <cooloney@kernel.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Acked-by: default avatarPaul Mundt <lethal@linux-sh.org>
      Cc: Greg Ungerer <gerg@uclinux.org>
      Signed-off-by: default avatarJohannes Weiner <jw@emlix.com>
      Acked-by: default avatarMike Frysinger <vapier.adi@gmail.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      c3dc5bec
    • Russell King's avatar
      [ARM] update mach-types · 6daad5c6
      Russell King authored
      
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      6daad5c6
  7. 28 May, 2009 3 commits
    • Mathieu Desnoyers's avatar
      [ARM] Add cmpxchg support for ARMv6+ systems (v5) · ecd322c9
      Mathieu Desnoyers authored
      
      
      Add cmpxchg/cmpxchg64 support for ARMv6K and ARMv7 systems
      (original patch from Catalin Marinas <catalin.marinas@arm.com>)
      
      The cmpxchg and cmpxchg64 functions can be implemented using the
      LDREX*/STREX* instructions. Since operand lengths other than 32bit are
      required, the full implementations are only available if the ARMv6K
      extensions are present (for the LDREXB, LDREXH and LDREXD instructions).
      
      For ARMv6, only 32-bits cmpxchg is available.
      
      Mathieu :
      
      Make cmpxchg_local always available with best implementation for all type sizes (1, 2, 4 bytes).
      Make cmpxchg64_local always available.
      
      Use "Ir" constraint for "old" operand, like atomic.h atomic_cmpxchg does.
      
      Change since v3 :
      - Add "memory" clobbers (thanks to Nicolas Pitre)
      - removed __asmeq(), only needed for old compilers, very unlikely on ARMv6+.
      
      Note : ARMv7-M should eventually be ifdefed-out of cmpxchg64. But it's not
      supported by the Linux kernel currently.
      
      Put back arm < v6 cmpxchg support.
      Signed-off-by: default avatarMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
      CC: Catalin Marinas <catalin.marinas@arm.com>
      CC: Nicolas Pitre <nico@cam.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ecd322c9
    • Russell King's avatar
      [ARM] barriers: improve xchg, bitops and atomic SMP barriers · bac4e960
      Russell King authored
      
      
      Mathieu Desnoyers pointed out that the ARM barriers were lacking:
      
      - cmpxchg, xchg and atomic add return need memory barriers on
        architectures which can reorder the relative order in which memory
        read/writes can be seen between CPUs, which seems to include recent
        ARM architectures. Those barriers are currently missing on ARM.
      
      - test_and_xxx_bit were missing SMP barriers.
      
      So put these barriers in.  Provide separate atomic_add/atomic_sub
      operations which do not require barriers.
      Reported-Reviewed-and-Acked-by: default avatarMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      bac4e960
    • Paulius Zaleckas's avatar
  8. 27 May, 2009 8 commits
  9. 26 May, 2009 7 commits
  10. 25 May, 2009 3 commits
    • Avi Kivity's avatar
      KVM: Fix PDPTR reloading on CR4 writes · a2edf57f
      Avi Kivity authored
      
      
      The processor is documented to reload the PDPTRs while in PAE mode if any
      of the CR4 bits PSE, PGE, or PAE change.  Linux relies on this
      behaviour when zapping the low mappings of PAE kernels during boot.
      
      The code already handled changes to CR4.PAE; augment it to also notice changes
      to PSE and PGE.
      
      This triggered while booting an F11 PAE kernel; the futex initialization code
      runs before any CR3 reloads and writes to a NULL pointer; the futex subsystem
      ended up uninitialized, killing PI futexes and pulseaudio which uses them.
      
      Cc: stable@kernel.org
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      a2edf57f
    • Avi Kivity's avatar
      KVM: Make paravirt tlb flush also reload the PAE PDPTRs · a8cd0244
      Avi Kivity authored
      
      
      The paravirt tlb flush may be used not only to flush TLBs, but also
      to reload the four page-directory-pointer-table entries, as it is used
      as a replacement for reloading CR3.  Change the code to do the entire
      CR3 reloading dance instead of simply flushing the TLB.
      
      Cc: stable@kernel.org
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      a8cd0244
    • Tejun Heo's avatar
      x86: Remove remap percpu allocator for the time being · 71c9d8b6
      Tejun Heo authored
      Remap percpu allocator has subtle bug when combined with page
      attribute changing.  Remap percpu allocator aliases PMD pages for the
      first chunk and as pageattr doesn't know about the alias it ends up
      updating page attributes of the original mapping thus leaving the
      alises in inconsistent state which might lead to subtle data
      corruption.  Please read the following threads for more information:
      
        http://thread.gmane.org/gmane.linux.kernel/835783
      
      The following is the proposed fix which teaches pageattr about percpu
      aliases.
      
        http://thread.gmane.org/gmane.linux.kernel/837157
      
      
      
      However, the above changes are deemed too pervasive for upstream
      inclusion for 2.6.30 release, so this patch essentially disables
      the remap allocator for the time being.
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      LKML-Reference: <4A1A0A27.4050301@kernel.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      71c9d8b6
  11. 23 May, 2009 1 commit
  12. 22 May, 2009 5 commits