1. 19 May, 2009 7 commits
  2. 15 May, 2009 1 commit
  3. 14 May, 2009 1 commit
  4. 08 May, 2009 1 commit
  5. 21 Apr, 2009 1 commit
    • Anton Vorontsov's avatar
      fsl_rio: Pass the proper device to dma mapping routines · 0dbbbf1a
      Anton Vorontsov authored
      The driver should pass a device that specifies internal DMA ops, but
      currently NULL pointer is passed, therefore following bug appears
      during boot up:
        ------------[ cut here ]------------
        Kernel BUG at c0018a7c [verbose debug info unavailable]
        Oops: Exception in kernel mode, sig: 5 [#1]
        NIP [c0018a7c] fsl_rio_doorbell_init+0x34/0x60
        LR [c0018a70] fsl_rio_doorbell_init+0x28/0x60
        Call Trace:
        [ef82bda0] [c0018a70] fsl_rio_doorbell_init+0x28/0x60 (unreliable)
        [ef82bdc0] [c0019160] fsl_rio_setup+0x6b8/0x84c
        [ef82be20] [c02d28ac] fsl_of_rio_rpn_probe+0x30/0x50
        [ef82be40] [c0234f20] of_platform_device_probe+0x5c/0x84
        ---[ end trace 561bb236c800851f ]---
      This patch fixes the issue.
      Signed-off-by: default avatarAnton Vorontsov <avorontsov@ru.mvista.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  6. 06 Apr, 2009 2 commits
  7. 01 Apr, 2009 2 commits
  8. 30 Mar, 2009 2 commits
  9. 24 Mar, 2009 3 commits
  10. 19 Mar, 2009 1 commit
  11. 09 Mar, 2009 2 commits
  12. 26 Feb, 2009 1 commit
  13. 14 Feb, 2009 1 commit
  14. 06 Feb, 2009 2 commits
  15. 29 Jan, 2009 2 commits
  16. 13 Jan, 2009 1 commit
  17. 12 Jan, 2009 1 commit
  18. 07 Jan, 2009 2 commits
    • Trent Piepho's avatar
      powerpc/fsl-pci: Set relaxed ordering on prefetchable ranges · 565f3764
      Trent Piepho authored
      Provides a small speedup when accessing pefetchable ranges.  To indicate
      that a memory range is prefetchable, mark it in the dts file with 42000000
      instead of 02000000.
      A powepc pci_controller is allowed three memory ranges, any of which may be
      prefetchable.  However, the PCI-PCI bridge configuration space only has one
      field for "non-prefetchable memory behind bridge", which has a 32 bit
      address, and one field for "prefetchable memory behind bridge", which may
      have a 64 bit address.  These are PCI bus addresses, not CPU physical
      So really you're only allowed one memory range of each type.  And if you
      want the range at a PCI address above 32 bits you must make it
      Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Trent Piepho's avatar
      powerpc/fsl-pci: Better ATMU setup for 85xx/86xx · a097a78c
      Trent Piepho authored
      The code that sets up the outbound ATMU windows, which is used to map CPU
      physical addresses into PCI bus addresses where BARs will be mapped, didn't
      work so well.
      For one, it leaked the ioremap() of the ATMU registers.  Another small bug
      was the high 20 bits of the PCI bus address were left as zero.  It's legal
      for prefetchable memory regions to be above 32 bits, so the high 20 bits
      might not be zero.
      Mainly, it couldn't handle ranges that were not a power of two in size or
      were not naturally aligned.  The ATMU windows have these requirements (size
      & alignment), but the code didn't bother to check if the ranges it was
      programming met them.  If they didn't, the windows would silently be
      programmed incorrectly.
      This new code can handle ranges which are not power of two sized nor
      naturally aligned.  It simply splits the ranges into multiple valid ATMU
      windows.  As there are only four windows, pooly aligned or sized ranges
      (which didn't even work before) may run out of windows.  In this case an
      error is printed and an effort is made to disable the unmapped resources.
      An improvement that could be made would be to make use of the default
      outbound window.  Iff hose->pci_mem_offset is zero, then it's possible that
      some or all of the ranges might not need an outbound window and could just
      use the default window.
      The default ATMU window can support a pci_mem_offset less than zero too,
      but pci_mem_offset is unsigned.  One could say the abilities allowed a
      powerpc pci_controller is neither subset nor a superset of the abilities of
      a Freescale PCIe controller.  Thankfully, the most useful bits are in the
      intersection of the two abilities.
      Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  19. 30 Dec, 2008 5 commits
  20. 21 Dec, 2008 2 commits