1. 05 Apr, 2016 15 commits
  2. 04 Apr, 2016 24 commits
  3. 03 Apr, 2016 1 commit
    • David S. Miller's avatar
      Merge branch 'stmmac-GMAC4.x' · 833716e0
      David S. Miller authored
      Alexandre TORGUE says:
      Enhance stmmac driver to support GMAC4.x IP
      This is a subset of patch to enhance current stmmac driver to support
      new GMAC4.x chips. New set of callbacks is defined to support this new
      family: descriptors, dma, core.
      One of main changes of GMAC 4.xx IP is descriptors management.
       -descriptors are only used in ring mode.
       -A descriptor is composed of 4 32bits registers (no more extended
       -descriptor mechanism (Tx for example, but it is exactly the same for RX):
       -useful registers:
        -DMA_CH#_TxDesc_Ring_Len: length of transmit descriptor ring
        -DMA_CH#_TxDesc_List_Address: start address of the ring
        -DMA_CH#_TxDesc_Tail_Pointer: address of the last descriptor to send + 1.
        -DMA_CH#_TxDesc_Current_App_TxDesc: address of the current descriptor
       -The descriptor Tail Pointer register contains the pointer to the
        descriptor address (N). The base address and the current
        descriptor decide the address of the current descriptor that the
        DMA can process. The descriptors up to one location less than the
        one indicated by the descriptor tail pointer (N-1) are owned by
        the DMA. The DMA continues to process the descriptors until the
        following condition occurs:
        "current descriptor pointer == Descriptor Tail pointer"
        Then the DMA goes into suspend mode. The application must perform
        a write to descriptor tail pointer register and update the tail
        pointer to have the following condition and to start a new transfer:
        "current descriptor pointer < Descriptor tail pointer"
        The DMA automatically wraps around the base address when the end
        of ring is reached.
      New features are available on IP:
       -TSO (TCP Segmentation Offload) for TX only
       -Split header: to have header and payload in 2 different buffers (not yet implemented)
      Below some throughput figures obtained on some boxes:
                              iperf (mbps)
                             tcp     udp
                          tx   rx   tx  rx
          GMAC4.x         935  930  750 800
      Note: There is a change in 4.10a databook on bitfield mapping of DMA_CHANx_INTR_ENA register.
      This requires to have é diffrent set of callbacks between IP 4.00a and 4.10a.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>