1. 26 Apr, 2013 22 commits
    • Gavin Shan's avatar
      powerpc/powernv: TCE invalidation for PHB3 · 4cce9550
      Gavin Shan authored
      
      
      The TCE should be invalidated while it's created or free'd. The
      approach to do that for IODA1 and IODA2 compliant PHBs are different.
      So the patch differentiate them with different functions called to
      do that for IODA1 and IODA2 compliant PHBs. It's notable that the
      PCI address is used to invalidate the corresponding TCE on IODA2
      compliant PHB3.
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      4cce9550
    • Gavin Shan's avatar
      powerpc/powernv: Patch MSI EOI handler on P8 · 137436c9
      Gavin Shan authored
      
      
      The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
      steps to handle the P/Q bits in IVE before EOIing the corresponding
      interrupt. The patch changes the EOI handler to cover that. we have
      individual IRQ chip in each PHB instance. During the MSI IRQ setup
      time, the IRQ chip is copied over from the original one for that IRQ,
      and the EOI handler is patched with the one that will handle the P/Q
      bits (As Ben suggested).
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      137436c9
    • Gavin Shan's avatar
      powerpc/powernv: Add option CONFIG_POWERNV_MSI · a486bdb0
      Gavin Shan authored
      
      
      As Michael Ellerman suggested, to add CONFIG_POWERNV_MSI for PowerNV
      platform. That's similar to CONFIG_PSERIES_MSI for pSeries platform.
      For now, we don't make it dependent on CONFIG_EEH since it's not ready
      to enable that yet.
      
      Apart from that, we also enable CONFIG_PPC_MSI_BITMAP on selecting
      CONFIG_POWERNV_MSI.
      Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a486bdb0
    • Gavin Shan's avatar
      powerpc/powernv: Supports PHB3 · aa0c033f
      Gavin Shan authored
      
      
      The patch intends to initialize PHB3 during system boot stage. The
      flag "PNV_PHB_MODEL_PHB3" is introduced to differentiate IODA2
      compatible PHB3 from other types of PHBs.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      aa0c033f
    • Paul Mackerras's avatar
      powerpc: Fix "attempt to move .org backwards" error · a485c709
      Paul Mackerras authored
      
      
      Building a 64-bit powerpc kernel with PR KVM enabled currently gives
      this error:
      
        AS      arch/powerpc/kernel/head_64.o
      arch/powerpc/kernel/exceptions-64s.S: Assembler messages:
      arch/powerpc/kernel/exceptions-64s.S:258: Error: attempt to move .org backwards
      make[2]: *** [arch/powerpc/kernel/head_64.o] Error 1
      
      This happens because the MASKABLE_EXCEPTION_PSERIES macro turns into
      33 instructions, but we only have space for 32 at the decrementer
      interrupt vector (from 0x900 to 0x980).
      
      In the code generated by the MASKABLE_EXCEPTION_PSERIES macro, we
      currently have two instances of the HMT_MEDIUM macro, which has the
      effect of setting the SMT thread priority to medium.  One is the
      first instruction, and is overwritten by a no-op on processors where
      we save the PPR (processor priority register), that is, POWER7 or
      later.  The other is after we have saved the PPR.
      
      In order to reduce the code at 0x900 by one instruction, we omit the
      first HMT_MEDIUM.  On processors without SMT this will have no effect
      since HMT_MEDIUM is a no-op there.  On POWER5 and RS64 machines this
      will mean that the first few instructions take a little longer in the
      case where a decrementer interrupt occurs when the hardware thread is
      running at low SMT priority.  On POWER6 and later machines, the
      hardware automatically boosts the thread priority when a decrementer
      interrupt is taken if the thread priority was below medium, so this
      change won't make any difference.
      
      The alternative would be to branch out of line after saving the CFAR.
      However, that would incur an extra overhead on all processors, whereas
      the approach adopted here only adds overhead on older threaded processors.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a485c709
    • Nathan Fontenot's avatar
      powerpc/pseries: Add /proc interface to control topology updates · e04fa612
      Nathan Fontenot authored
      
      
      There are instances in which we do not want topology updates to occur.
      In order to allow this a /proc interface (/proc/powerpc/topology_updates)
      is introduced so that topology updates can be enabled and disabled.
      
      This patch also adds a prrn_is_enabled() call so that PRRN events are
      handled in the kernel only if topology updating is enabled.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e04fa612
    • Nathan Fontenot's avatar
      powerpc/pseries: Enable PRRN handling · 1b1218d3
      Nathan Fontenot authored
      
      
      The Linux kernel and platform firmware negotiate their mutual support
      of the PRRN option via the ibm,client-architecture-support interface.
      This patch simply sets the appropriate fields in the client architecture
      vector to indicate Linux support for PRRN and will allow the firmware to
      report PRRN events via the RTAS event-scan mechanism.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      1b1218d3
    • Jesse Larrew's avatar
      powerpc/pseries: RE-enable Virtual Processor Home Node updating · b7abef04
      Jesse Larrew authored
      
      
      The new PRRN firmware feature provides a more convenient and event-driven
      interface than VPHN for notifying Linux of changes to the NUMA affinity of
      platform resources. However, for practical reasons, it may not be feasible
      for some customers to update to the latest firmware. For these customers,
      the VPHN feature supported on previous firmware versions may still be the
      best option.
      
      The VPHN feature was previously disabled due to races with the load
      balancing code when accessing the NUMA cpu maps, but the new stop_machine()
      approach protects the NUMA cpu maps from these concurrent accesses. It
      should be safe to re-enable this feature now.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      b7abef04
    • Jesse Larrew's avatar
      powerpc/pseries: Update NUMA VDSO information when updating CPU maps · 176bbf14
      Jesse Larrew authored
      The following patch adds vdso_getcpu_init(), which stores the NUMA node for
      a cpu in SPRG3:
      
      Commit 18ad51dd
      
       ("powerpc: Add VDSO version of getcpu") adds
      vdso_getcpu_init(), which stores the NUMA node for a cpu in SPRG3.
      
      This patch ensures that this information is also updated when the NUMA
      affinity of a cpu changes.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      176bbf14
    • Nathan Fontenot's avatar
      powerpc/pseries: Use stop machine to update cpu maps · 30c05350
      Nathan Fontenot authored
      
      
      The new PRRN firmware feature allows CPU and memory resources to be
      transparently reassigned across NUMA boundaries. When this happens, the
      kernel must update the node maps to reflect the new affinity information.
      
      Although the NUMA maps can be protected by locking primitives during the
      update itself, this is insufficient to prevent concurrent accesses to these
      structures. Since cpumask_of_node() hands out a pointer to these
      structures, they can still be modified outside of the lock. Furthermore,
      tracking down each usage of these pointers and adding locks would be quite
      invasive and difficult to maintain.
      
      The approach used is to make a list of affected cpus and call stop_machine
      to have the update routine run on each of the affected cpus allowing them
      to update themselves. Each cpu finds itself in the list of cpus and makes
      the appropriate updates. We need to have each cpu do this for themselves to
      handle calls to vdso_getcpu_init() added in a subsequent patch.
      
      Situations like these are best handled using stop_machine(). Since the NUMA
      affinity updates are exceptionally rare events, this approach has the
      benefit of not adding any overhead while accessing the NUMA maps during
      normal operation.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      30c05350
    • Jesse Larrew's avatar
      powerpc/pseries: Update CPU maps when device tree is updated · 5d88aa85
      Jesse Larrew authored
      
      
      Platform events such as partition migration or the new PRRN firmware
      feature can cause the NUMA characteristics of a CPU to change, and these
      changes will be reflected in the device tree nodes for the affected
      CPUs.
      
      This patch registers a handler for Open Firmware device tree updates
      and reconfigures the CPU and node maps whenever the associativity
      changes. Currently, this is accomplished by marking the affected CPUs in
      the cpu_associativity_changes_mask and allowing
      arch_update_cpu_topology() to retrieve the new associativity information
      using hcall_vphn().
      
      Protecting the NUMA cpu maps from concurrent access during an update
      operation will be addressed in a subsequent patch in this series.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      5d88aa85
    • Nathan Fontenot's avatar
      powerpc/pseries: Update numa.c to use updated firmware_has_feature() · 8002b0c5
      Nathan Fontenot authored
      
      
      Update the numa code to use the updated firmware_has_feature() when checking
      for type 1 affinity.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8002b0c5
    • Nathan Fontenot's avatar
      powerpc/pseries: Update firmware_has_feature() to check architecture vector 5 bits · f0ff7eb4
      Nathan Fontenot authored
      
      
      The firmware_has_feature() function makes it easy to check for supported
      features of the hypervisor. This patch extends the capability of
      firmware_has_feature() to include checking for specified bits
      in vector 5 of the architecture vector as reported in the device tree.
      
      As part of this the #defines used for the architecture vector are re-defined
      such that each option has the index into vector 5 and the feature bit encoded
      into it. This makes checking for architecture bits when initiating data
      for firmware_has_feature much easier.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      f0ff7eb4
    • Nathan Fontenot's avatar
      powerpc/pseries: Use ARRAY_SIZE to iterate over firmware_features_table array · 43c0ea60
      Nathan Fontenot authored
      
      
      When iterating over the entries in firmware_features_table we only need
      to go over the actual number of entries in the array instead of declaring
      it to be bigger and checking to make sure there is a valid entry in every
      slot.
      
      This patch removes the FIRMWARE_MAX_FEATURES #define and replaces the
      array looping with the use of ARRAY_SIZE().
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      43c0ea60
    • Nathan Fontenot's avatar
      powerpc/pseries: Move architecture vector definitions to prom.h · 530b5e14
      Nathan Fontenot authored
      
      
      As part of handling of PRRN events we need to check vector 5 of the
      architecture vector bits reported in the device tree to ensure PRRN event
      handling is enabled. To do this firmware_has_feature() is updated (in a
      subsequent patch) to make this check vector 5 bits. To avoid having to
      re-define bits in the architecture vector the bit definitions are moved
      to prom.h.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      530b5e14
    • Jesse Larrew's avatar
      powerpc/pseries: Add PRRN RTAS event handler · 49c68a85
      Jesse Larrew authored
      
      
      A PRRN event is signaled via the RTAS event-scan mechanism, which
      returns a Hot Plug Event message "fixed part" indicating "Platform
      Resource Reassignment". In response to the Hot Plug Event message,
      we must call ibm,update-nodes to determine which resources were
      reassigned and then ibm,update-properties to obtain the new affinity
      information about those resources.
      
      The PRRN event-scan RTAS message contains only the "fixed part" with
      the "Type" field set to the value 160 and no Extended Event Log. The
      four-byte Extended Event Log Length field is re-purposed (since no
      Extended Event Log message is included) to pass the "scope" parameter
      that causes the ibm,update-nodes to return the nodes affected by the
      specific resource reassignment.
      
      This patch adds a handler for RTAS events. The function
      pseries_devicetree_update() (from mobility.c) is used to make the
      ibm,update-nodes/ibm,update-properties RTAS calls. Updating the NUMA maps
      (handled by a subsequent patch) will require significant processing,
      so pseries_devicetree_update() is called from an asynchronous workqueue
      to allow event processing to continue.
      
      PRRN RTAS events on pseries systems are rare events that have to be
      initiated from the HMC console for the system by an IBM tech. This allows
      us to assume that these events are widely spaced. Additionally, all work
      on the queue is flushed before handling any new work to ensure we only have
      one event in flight being handled at a time.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      49c68a85
    • Nathan Fontenot's avatar
      powerpc/pseries: Correct buffer parsing in update_dt_node() · 2e9b7b02
      Nathan Fontenot authored
      
      
      Correct parsing of the buffer returned from ibm,update-properties. The first
      element is a length and the path to the property which is slightly different
      from the list of properties in the buffer so we need to specifically
      handle this.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      2e9b7b02
    • Nathan Fontenot's avatar
      powerpc/pseries: Expose pseries devicetree_update() · 762ec157
      Nathan Fontenot authored
      
      
      Newer firmware on Power systems can transparently reassign platform resources
      (CPU and Memory) in use. For instance, if a processor or memory unit is
      predicted to fail, the platform may transparently move the processing to an
      equivalent unused processor or the memory state to an equivalent unused
      memory unit. However, reassigning resources across NUMA boundaries may alter
      the performance of the partition. When such reassignment is necessary, the
      Platform Resource Reassignment Notification (PRRN) option provides a
      mechanism to inform the Linux kernel of changes to the NUMA affinity of
      its platform resources.
      
      When rtasd receives a PRRN event, it needs to make a series of RTAS
      calls (ibm,update-nodes and ibm,update-properties) to retrieve the
      updated device tree information. These calls are already handled in the
      pseries_devicetree_update() routine used in partition migration.
      
      This patch exposes pseries_devicetree_update() to make it accessible
      to other pseries routines, this patch also updates pseries_devicetree_update()
      to take a 32-bit scope parameter. The scope value, which was previously hard
      coded to 1 for partition migration, is used for the RTAS calls
      ibm,update-nodes/properties to update the device tree.
      Signed-off-by: default avatarNathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      762ec157
    • Michael Neuling's avatar
      powerpc: Fix hardware IRQs with MMU on exceptions when HV=0 · 3e96ca7f
      Michael Neuling authored
      
      
      POWER8 allows us to take interrupts with the MMU on.  This gives us a
      second set of vectors offset at 0x4000.
      
      Unfortunately when coping these vectors we missed checking for MSR HV
      for hardware interrupts (0x500).  This results in us trying to use
      HSRR0/1 when HV=0, rather than SRR0/1 on HW IRQs
      
      The below fixes this to check CPU_FTR_HVMODE when patching the code at
      0x4500.
      
      Also we remove the check for CPU_FTR_ARCH_206 since relocation on IRQs
      are only available in arch 2.07 and beyond.
      
      Thanks to benh for helping find this.
      Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
      CC: <stable@vger.kernel.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3e96ca7f
    • Michael Neuling's avatar
      powerpc/power8: Fix secondary CPUs hanging on boot for HV=0 · 8c2a3817
      Michael Neuling authored
      
      
      In __restore_cpu_power8 we determine if we are HV and if not, we return
      before setting HV only resources.
      
      Unfortunately we forgot to restore the link register from r11 before
      returning.
      
      This will happen on boot and with secondary CPUs not coming online.
      
      This adds the missing link register restore.
      Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
      CC: <stable@vger.kernel.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8c2a3817
    • Michael Neuling's avatar
      powerpc: Add isync to copy_and_flush · 29ce3c50
      Michael Neuling authored
      
      
      In __after_prom_start we copy the kernel down to zero in two calls to
      copy_and_flush.  After the first call (copy from 0 to copy_to_here:)
      we jump to the newly copied code soon after.
      
      Unfortunately there's no isync between the copy of this code and the
      jump to it.  Hence it's possible that stale instructions could still be
      in the icache or pipeline before we branch to it.
      
      We've seen this on real machines and it's results in no console output
      after:
        calling quiesce...
        returning from prom_init
      
      The below adds an isync to ensure that the copy and flushing has
      completed before any branching to the new instructions occurs.
      Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
      CC: <stable@vger.kernel.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      29ce3c50
    • Michael Neuling's avatar
      powerpc: Add HWCAP2 aux entry · 2171364d
      Michael Neuling authored
      
      
      We are currently out of free bits in AT_HWCAP. With POWER8, we have
      several hardware features that we need to advertise.
      
      Tested on POWER and x86.
      Signed-off-by: default avatarMichael Neuling <michael@neuling.org>
      Signed-off-by: default avatarNishanth Aravamudan <nacc@linux.vnet.ibm.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      2171364d
  2. 24 Apr, 2013 5 commits
  3. 23 Apr, 2013 3 commits
  4. 18 Apr, 2013 10 commits
    • Li Zhong's avatar
      powerpc: Try to insert the hptes repeatedly in kernel_map_linear_page() · 016af59f
      Li Zhong authored
      
      
      This patch fixes the following oops, which could be trigged by build the kernel
      with many concurrent threads, under CONFIG_DEBUG_PAGEALLOC.
      
      hpte_insert() might return -1, indicating that the bucket (primary here)
      is full. We are not necessarily reporting a BUG in this case. Instead, we could
      try repeatedly (try secondary, remove and try again) until we find a slot.
      
      [  543.075675] ------------[ cut here ]------------
      [  543.075701] kernel BUG at arch/powerpc/mm/hash_utils_64.c:1239!
      [  543.075714] Oops: Exception in kernel mode, sig: 5 [#1]
      [  543.075722] PREEMPT SMP NR_CPUS=16 DEBUG_PAGEALLOC NUMA pSeries
      [  543.075741] Modules linked in: binfmt_misc ehea
      [  543.075759] NIP: c000000000036eb0 LR: c000000000036ea4 CTR: c00000000005a594
      [  543.075771] REGS: c0000000a90832c0 TRAP: 0700   Not tainted  (3.8.0-next-20130222)
      [  543.075781] MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI>  CR: 22224482  XER: 00000000
      [  543.075816] SOFTE: 0
      [  543.075823] CFAR: c00000000004c200
      [  543.075830] TASK = c0000000e506b750[23934] 'cc1' THREAD: c0000000a9080000 CPU: 1
      GPR00: 0000000000000001 c0000000a9083540 c000000000c600a8 ffffffffffffffff
      GPR04: 0000000000000050 fffffffffffffffa c0000000a90834e0 00000000004ff594
      GPR08: 0000000000000001 0000000000000000 000000009592d4d8 c000000000c86854
      GPR12: 0000000000000002 c000000006ead300 0000000000a51000 0000000000000001
      GPR16: f000000003354380 ffffffffffffffff ffffffffffffff80 0000000000000000
      GPR20: 0000000000000001 c000000000c600a8 0000000000000001 0000000000000001
      GPR24: 0000000003354380 c000000000000000 0000000000000000 c000000000b65950
      GPR28: 0000002000000000 00000000000cd50e 0000000000bf50d9 c000000000c7c230
      [  543.076005] NIP [c000000000036eb0] .kernel_map_pages+0x1e0/0x3f8
      [  543.076016] LR [c000000000036ea4] .kernel_map_pages+0x1d4/0x3f8
      [  543.076025] Call Trace:
      [  543.076033] [c0000000a9083540] [c000000000036ea4] .kernel_map_pages+0x1d4/0x3f8 (unreliable)
      [  543.076053] [c0000000a9083640] [c000000000167638] .get_page_from_freelist+0x6cc/0x8dc
      [  543.076067] [c0000000a9083800] [c000000000167a48] .__alloc_pages_nodemask+0x200/0x96c
      [  543.076082] [c0000000a90839c0] [c0000000001ade44] .alloc_pages_vma+0x160/0x1e4
      [  543.076098] [c0000000a9083a80] [c00000000018ce04] .handle_pte_fault+0x1b0/0x7e8
      [  543.076113] [c0000000a9083b50] [c00000000018d5a8] .handle_mm_fault+0x16c/0x1a0
      [  543.076129] [c0000000a9083c00] [c0000000007bf1dc] .do_page_fault+0x4d0/0x7a4
      [  543.076144] [c0000000a9083e30] [c0000000000090e8] handle_page_fault+0x10/0x30
      [  543.076155] Instruction dump:
      [  543.076163] 7c630038 78631d88 e80a0000 f8410028 7c0903a6 e91f01de e96a0010 e84a0008
      [  543.076192] 4e800421 e8410028 7c7107b4 7a200fe0 <0b000000> 7f63db78 48785781 60000000
      [  543.076224] ---[ end trace bd5807e8d6ae186b ]---
      Signed-off-by: default avatarLi Zhong <zhong@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      016af59f
    • Li Zhong's avatar
      powerpc: Split the code trying to insert hpte repeatedly as an helper function · b170bd3d
      Li Zhong authored
      
      
      Move the logic trying to insert hpte in __hash_page_huge() to an helper
      function, so it could also be used by others.
      Signed-off-by: default avatarLi Zhong <zhong@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      b170bd3d
    • Li Zhong's avatar
      powerpc: Move the setting of rflags out of loop in __hash_page_huge · 2c3c0693
      Li Zhong authored
      
      
      It seems that new_pte and rflags don't get changed in the repeating loop, so
      move their assignment out of the loop.
      Signed-off-by: default avatarLi Zhong <zhong@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      2c3c0693
    • Brian King's avatar
      powerpc: Set default VGA device · c2e1d845
      Brian King authored
      
      
      Add a PCI quirk for VGA devices on Power to set the default VGA device.
      Ensures a default VGA is always set if a graphics adapter is present,
      even if firmware did not initialize it. If more than one graphics
      adapter is present, ensure the one initialized by firmware is set
      as the default VGA device. This ensures that X autoconfiguration
      will work.
      Signed-off-by: default avatarBrian King <brking@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      c2e1d845
    • Yuanquan Chen's avatar
      powerpc/pci: fix PCI-e devices rescan issue on powerpc platform · 37f02195
      Yuanquan Chen authored
      
      
      Powerpc initializes the DMA and IRQ information in pci_scan_child_bus()->
      pcibios_fixup_bus()->pcibios_setup_bus_devices(). But for the devices
      which are hotpluged, bus->is added has been set for the first scan of the
      PCI-e bus, so the initialization code won't be called. Then the hotpluged
      devices' driver will fail to load.
      
      For example :
      The PCI-e device 0001:03:00.0 is the Intel PCI-e e1000e network card, remove
      it from the system:
      
          # echo 1 > /sys/bus/pci/devices/0001\:03\:00.0/remove
          # e1000e 0001:03:00.0 eth0: removed PHC
      
      Rescan it from it's bus:
      
          # echo 1 > /sys/bus/pci/devices/0001\:02\:00.0/rescan
          ...
          e1000e 0001:03:00.0: Disabling ASPM L0s L1
          e1000e 0001:03:00.0: No usable DMA configuration, aborting
          e1000e: probe of 0001:03:00.0 failed with error -5
      
      So we move the DMA & IRQ initialization code from pcibios_setup_devices() and
      construct a new function pcibios_enable_device. We call this function in
      pcibios_enable_device, which will be called by PCI-e rescan code. At the
      meanwhile, we avoid the the impact on cardbus. I also validate this patch with
      silicon's PCIe-sata which encounters the IRQ issue.
      Signed-off-by: default avatarYuanquan Chen <Yuanquan.Chen@freescale.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Hiroo Matsumoto <matsumoto.hiroo@jp.fujitsu.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      37f02195
    • Stephen Rothwell's avatar
      powerpc: fix annotation of fake_numa_create_new_node() · 55671f3c
      Stephen Rothwell authored
      
      
      This function has always been marked as __cpuinit, but is only called
      from functions marked as __init and references an __initdata variable.
      So change its annotation to __init.
      
      Fixes this build warning:
      
      WARNING: arch/powerpc/mm/built-in.o(.cpuinit.text+0x86): Section mismatch in reference from the function .fake_numa_create_new_node() to the variable .init.data:cmdline
      The function __cpuinit .fake_numa_create_new_node() references
      a variable __initdata cmdline.
      If cmdline is only used by .fake_numa_create_new_node then
      annotate cmdline with a matching annotation.
      Signed-off-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      55671f3c
    • Vaidyanathan Srinivasan's avatar
      powerpc: fix numa distance for form0 device tree · 7122beee
      Vaidyanathan Srinivasan authored
      The following commit breaks numa distance setup for old powerpc
      systems that use form0 encoding in device tree.
      
      commit 41eab6f8
      
      
      powerpc/numa: Use form 1 affinity to setup node distance
      
      Device tree node /rtas/ibm,associativity-reference-points would
      index into /cpus/PowerPCxxxx/ibm,associativity based on form0 or
      form1 encoding detected by ibm,architecture-vec-5 property.
      
      All modern systems use form1 and current kernel code is correct.
      However, on older systems with form0 encoding, the numa distance
      will get hard coded as LOCAL_DISTANCE for all nodes.  This causes
      task scheduling anomaly since scheduler will skip building numa
      level domain (topmost domain with all cpus) if all numa distances
      are same.  (value of 'level' in sched_init_numa() will remain 0)
      
      Prior to the above commit:
      ((from) == (to) ? LOCAL_DISTANCE : REMOTE_DISTANCE)
      
      Restoring compatible behavior with this patch for old powerpc systems
      with device tree where numa distance are encoded as form0.
      Signed-off-by: default avatarVaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      7122beee
    • Michael Neuling's avatar
      powerpc/ptrace: Add DAWR debug feature info for userspace · 517b7314
      Michael Neuling authored
      
      
      This adds new debug feature information so that the DAWR can be
      identified by userspace tools like GDB.
      
      Unfortunately the DAWR doesn't sit nicely into the current description
      that ptrace provides to userspace via struct ppc_debug_info.  It doesn't
      allow for specifying that only some ranges are possible or even the end
      alignment constraints (DAWR only allows 512 byte wide ranges which can't
      cross a 512 byte boundary).
      
      After talking to Edjunior Machado (GDB ppc developer), it was decided
      this was the best approach.  Just mark it as debug feature DAWR and
      tools like GDB can internally decide the constraints.
      Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      517b7314
    • Ian Munsie's avatar
      powerpc: Add accounting for Doorbell interrupts · a6a058e5
      Ian Munsie authored
      
      
      This patch adds a new line to /proc/interrupts to account for the
      doorbell interrupts that each hardware thread has received. The total
      interrupt count in /proc/stat will now also include doorbells.
      
       # cat /proc/interrupts
                 CPU0       CPU1       CPU2       CPU3
       16:        551       1267        281        175      XICS Level     IPI
      LOC:       2037       1503       1688       1625   Local timer interrupts
      SPU:          0          0          0          0   Spurious interrupts
      CNT:          0          0          0          0   Performance monitoring interrupts
      MCE:          0          0          0          0   Machine check exceptions
      DBL:         42        550         20         91   Doorbell interrupts
      Signed-off-by: default avatarIan Munsie <imunsie@au1.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      a6a058e5
    • Nishanth Aravamudan's avatar
      powerpc/pseries: close DDW race between functions of adapter · 61435690
      Nishanth Aravamudan authored
      
      
      Given a PCI device with multiple functions in a DDW capable slot, the
      following situation can be encountered: When the first function sets a
      64-bit DMA mask, enable_ddw() will be called and we can fail to properly
      configure DDW (the most common reason being the new DMA window's size is
      not large enough to map all of an LPAR's memory). With the recent
      changes to DDW, we remove the base window in order to determine if the
      new window is of sufficient size to cover an LPAR's memory. We correctly
      replace the base window if we find that not to be the case. However,
      once we go through and re-configured 32-bit DMA via the IOMMU, the next
      function of the adapter will go through the same process. And since DDW
      is a characteristic of the slot itself, we are most likely going to fail
      again. But to determine we are going to fail the second slot, we again
      remove the base window -- but that is now in-use by the first
      function/driver, which might be issuing I/O already.
      
      To close this window, keep a list of all the failed struct device_nodes
      that have failed to configure DDW. If the current device_node is in that
      list, just fail out immediately and fall back to 32-bit DMA without
      doing any DDW manipulation.
      Signed-off-by: default avatarNishanth Aravamudan <nacc@linux.vnet.ibm.com>
      Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
      61435690