1. 20 Aug, 2008 1 commit
  2. 04 Aug, 2008 1 commit
  3. 28 Jul, 2008 4 commits
  4. 25 Jul, 2008 2 commits
    • Michael Buesch's avatar
      gpiolib: allow user-selection · 7444a72e
      Michael Buesch authored
      This patch adds functionality to the gpio-lib subsystem to make it
      possible to enable the gpio-lib code even if the architecture code didn't
      request to get it built in.
      The archtitecture code does still need to implement the gpiolib accessor
      functions in its asm/gpio.h file.  This patch adds the implementations for
      x86 and PPC.
      With these changes it is possible to run generic GPIO expansion cards on
      every architecture that implements the trivial wrapper functions.  Support
      for more architectures can easily be added.
      Signed-off-by: default avatarMichael Buesch <mb@bu3sch.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: David Brownell <david-b@pacbell.net>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jean Delvare <khali@linux-fr.org>
      Cc: Samuel Ortiz <sameo@openedhand.com>
      Cc: Kumar Gala <galak@gate.crashing.org>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Adrian Bunk <bunk@stusta.de>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    • Robert Jennings's avatar
      powerpc/pseries: iommu enablement for CMO · 6490c490
      Robert Jennings authored
      To support Cooperative Memory Overcommitment (CMO), we need to check
      for failure from some of the tce hcalls.
      These changes for the pseries platform affect the powerpc architecture;
      patches for the other affected platforms are included in this patch.
      pSeries platform IOMMU code changes:
       * platform TCE functions must handle H_NOT_ENOUGH_RESOURCES errors and
         return an error.
      Architecture IOMMU code changes:
       * Calls to ppc_md.tce_build need to check return values and return
         DMA_MAPPING_ERROR for transient errors.
      Architecture changes:
       * struct machdep_calls for tce_build*_pSeriesLP functions need to change
         to indicate failure.
       * all other platforms will need updates to iommu functions to match the new
         calling semantics; they will return 0 on success.  The other platforms
         default configs have been built, but no further testing was performed.
      Signed-off-by: default avatarRobert Jennings <rcj@linux.vnet.ibm.com>
      Acked-by: default avatarOlof Johansson <olof@lixom.net>
      Acked-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
  5. 22 Jul, 2008 3 commits
  6. 16 Jul, 2008 6 commits
  7. 14 Jul, 2008 2 commits
  8. 12 Jul, 2008 3 commits
  9. 26 Jun, 2008 2 commits
  10. 17 Jun, 2008 1 commit
    • Josh Boyer's avatar
      powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata · 5ce4b596
      Josh Boyer authored
      The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
      by looking for a zero value in the PCI cache line size register.  However,
      some drivers write to this register upon initialization.  This can cause
      MRMs to be used on these chips, which may cause deadlocks on PLB4.
      The workaround implemented here introduces a new indirect_type flag, called
      PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
      the pci fixup function for 4xx PCI bridges by determining if the bridge is
      compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
      function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
      zero, which will disable MRMs for these chips.
      A similar workaround has been tested by AMCC on various PCI cards, such as
      the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
      the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
      With the workaround in place, the card functioned properly and only Memory
      Reads were seen on the bus with the analyzer.
      Acked-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
  11. 11 Jun, 2008 2 commits
  12. 10 Jun, 2008 5 commits
  13. 09 Jun, 2008 4 commits
  14. 06 Jun, 2008 1 commit
  15. 03 Jun, 2008 1 commit
  16. 02 Jun, 2008 2 commits