- 04 Mar, 2011 1 commit
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Ben Skeggs authored
The nv30/nv40 3d driver is about to start using DMA_FENCE from the 3D object which, it turns out, doesn't like its DMA object to not be aligned to a 4KiB boundary. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 01 Mar, 2011 1 commit
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Jan Niehusmann authored
On a Thinkpad x61s, I noticed some memory corruption when plugging/unplugging the external VGA connection. The symptoms are that 4 bytes at the beginning of a page get overwritten by zeroes. The address of the corruption varies when rebooting the machine, but stays constant while it's running (so it's possible to repeatedly write some data and then corrupt it again by plugging the cable). Further investigation revealed that the corrupted address is (dev_priv->status_page_dmah->busaddr & 0xffffffff), ie. the beginning of the hardware status page of the i965 graphics card, cut to 32 bits. So it seems that for some memory access, the hardware uses only 32 bit addressing. If the hardware status page is located >4GB, this corrupts unrelated memory. Signed-off-by:
Jan Niehusmann <jan@gondor.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 28 Feb, 2011 2 commits
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Dave Airlie authored
This fixes CVE-2011-1013. Reported-by: Matthiew Herrb (OpenBSD X.org team) Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Ben Skeggs authored
Somehow fixes a misrendering + hang at GDM startup on my NVA8... My first guess would have been stale TLB entries laying around that a new bo then accidentally inherits. That doesn't make a great deal of sense however, as when we mapped the pages for the new bo the TLBs would've gotten flushed anyway. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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- 24 Feb, 2011 2 commits
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Chris Wilson authored
After disabling, we're meant to teardown the bo used for the contexts, not recurse into ourselves again and preventing module unload. Reported-and-tested-by:
Ben Widawsky <bwidawsk@gmail.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
It looks like gen2 has a peculiar interleaved 2-row inter-tile layout. Probably inherited from i81x which had 2kb tiles (which naturally fit an even-number-of-tile-rows scheme to fit onto 4kb pages). There is no other mention of this in any docs (also not in the Intel internal documention according to Chris Wilson). Problem manifests itself in corruptions in the second half of the last tile row (if the bo has an odd number of tiles). Which can only happen with relaxed tiling (introduced in a00b10c3). So reject set_tiling calls that don't satisfy this constrain to prevent broken userspace from causing havoc. While at it, also check the size for newer chipsets. LKML: https://lkml.org/lkml/2011/2/19/5 Reported-by:
Indan Zupancic <indan@nul.nu> Tested-by:
Indan Zupancic <indan@nul.nu> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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- 23 Feb, 2011 7 commits
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Dave Airlie authored
Some userspaces can emit a whole packet without disabling AA resolve by the looks of it, so we have to deal with them. Signed-off-by:
Dave Airlie <airlied@redhat.com> Tested-by:
Jorg Otte <jrg.otte@googlemail.com>
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Paul Bolle authored
r100_gpu_init() was dropped in 90aca4d2 ("drm/radeon/kms: simplify & improve GPU reset V2") but here it was only commented out. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Mario Kleiner authored
Testing showed the current code can already handle doublescan video modes just fine. A trivial tweak makes it work for interlaced scanout as well. Tested and shown to be precise on Radeon rv530, r600 and Intel 945-GME. Signed-off-by:
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Mario Kleiner authored
Documentation/atomic_ops.txt tells us that there are memory barriers optimized for atomic_inc and other atomic_t ops. Use these instead of smp_wmb(), and also to make the required memory barriers around vblank counter increments more explicit. Signed-off-by:
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Mario Kleiner authored
Use of abs() wrongly wrapped diff_ns to 32 bit, which gives a 1/4000 probability of a missed vblank increment at each vblank irq reenable if the kms driver doesn't support high precision vblank timestamping. Not a big deal in practice, but let's make it nice. Signed-off-by:
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
this aligns the height of the fb allocation so it doesn't trip over the size checks later when we use this from userspace to copy the buffer at X start. Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
This reverts commit a6f97617. Remove this commit as it is no longer necessary. The relevant bugs were fixed properly in: drm/radeon/kms: hopefully fix pll issues for real (v3) 5b40ddf8 drm/radeon/kms: add missing frac fb div flag for dce4+ 9f4283f4 This commit also broke certain ~5 Mhz modes on old arcade monitors, so reverting this commit fixes: https://bugzilla.kernel.org/show_bug.cgi?id=29502 Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 22 Feb, 2011 3 commits
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Jesse Barnes authored
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by:
Andy Whitcroft <apw@canonical.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Jesse Barnes authored
We can enable some safely, but FDI and transcoder interrupts can occur and block other interrupts from being detected (like port hotplug events). So keep them disabled by default (they can be re-enabled for debugging display bringup, but should generally be off). Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
If the gpu is hung, then whatever was inside the render cache is lost and there is little point waiting for it. Or complaining if we see an EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when we need to rewrite the registers for a new framebuffer, just ignore the error and proceed with the update. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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- 21 Feb, 2011 1 commit
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Indan Zupancic authored
The current code does not follow Intel documentation: It misses some things and does other, undocumented things. This causes wrong backlight values in certain conditions. Instead of adding tricky code handling badly documented and rare corner cases, don't handle combination mode specially at all. This way PCI_LBPC is never touched and weird things shouldn't happen. If combination mode is enabled, then the only downside is that changing the brightness has a greater granularity (the LBPC value), but LBPC is at most 254 and the maximum is in the thousands, so this is no real functional loss. A potential problem with not handling combined mode is that a brightness of max * PCI_LBPC is not bright enough. However, this is very unlikely because from the documentation LBPC seems to act as a scaling factor and doesn't look like it's supposed to be changed after boot. The value at boot should always result in a bright enough screen. IMPORTANT: However, although usually the above is true, it may not be when people ran an older (2.6.37) kernel which messed up the LBPC register, and they are unlucky enough to have a BIOS that saves and restores the LBPC value. Then a good kernel may seem to not work: Max brightness isn't bright enough. If this happens people should boot back into the old kernel, set brightness to the maximum, and then reboot. After that everything should be fine. For more information see the below links. This fixes bugs: http://bugzilla.kernel.org/show_bug.cgi?id=23472 http://bugzilla.kernel.org/show_bug.cgi?id=25072 Signed-off-by:
Indan Zupancic <indan@nul.nu> Tested-by:
Alex Riesen <raa.lkml@gmail.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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- 17 Feb, 2011 3 commits
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Alex Deucher authored
The fixed ref/post dividers are set by the AdjustPll table rather than the ss info table on dce4+. Make sure we enable the fractional feedback dividers when using a fixed post or ref divider on them as well. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=29272 Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Marek Olšák authored
Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Ben Skeggs authored
This has been broken since 2.6.37, and fixes resume on a couple of fermi boards I have access to. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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- 16 Feb, 2011 6 commits
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Ben Skeggs authored
We free the temporary binding before leaving this function, so we also have to wait for the move to actually complete. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Due to the default case handling the older chipsets, a bunch of the newer ones ended up having the wrong tiling regs used. This commit switches the default case to handle the newest chipsets. This also makes nv4e touch the "extra" tiling regs. "nv" doesn't touch them for C51 but traces of the NVIDIA binary driver show it being done there. I couldn't find NV41/NV45 traces to confirm the behaviour there, but an educated guess was taken at each of them. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
The DRM core fills this value, but at too late a stage for this to work, possibly resulting in an undesirable mode being selected. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Francisco Jerez authored
Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Francisco Jerez authored
Reported-by:
Alex Buell <alex.buell@munted.org.uk> Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Francisco Jerez authored
Reported-by:
Alex Buell <alex.buell@munted.org.uk> Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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- 14 Feb, 2011 10 commits
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Alex Deucher authored
The problematic boards have a recommended reference divider to be used when spread spectrum is enabled on the laptop panel. Enable the use of the recommended reference divider along with the new pll algo. v2: testing options v3: When using the fixed reference divider with LVDS, prefer min m to max p and use fractional feedback dividers. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28852 https://bugzilla.kernel.org/show_bug.cgi?id=24462 https://bugzilla.kernel.org/show_bug.cgi?id=26552 MacbookPro issues reported by Justin Mattock <justinmattock@gmail.com> Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Prevent divider overflow. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28932 Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Makes debugging CS rejections much easier. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Marek Olšák authored
This is an important security fix because we allowed arbitrary values to be passed to AARESOLVE_OFFSET. This also puts the right buffer address in the register. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Marek Olšák authored
Also move ZB_DEPTHCLEARVALUE to the list of safe regs. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Not only is linear aligned supposedly more performant, linear general is only supported by the CB in single slice mode. The texture hardware doesn't support linear general, but I think the hw automatically upgrades it to linear aligned. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Not only is linear aligned supposedly more performant, linear general is only supported by the CB in single slice mode. The texture hardware doesn't support linear general, but I think the hw automatically upgrades it to linear aligned. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
My evergreen has been in a remote PC for week and reset has never once saved me from certain doom, I finally relocated to the box with a serial cable and noticed an oops when the GPU resets, and the TTM delayed delete thread tries to remove something from the GTT. This stops the delayed delete thread from executing across the GPU reset handler, and woot I can GPU reset now. Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Based on 6xx/7xx endian fixes from Cédric Cano. v2: fix typo in shader Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 13 Feb, 2011 4 commits
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Cédric Cano authored
agd5f: minor cleanups Signed-off-by:
Cédric Cano <ccano@interfaceconcept.com> Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Cédric Cano authored
agd5f: additional cleanups/fixes Signed-off-by:
Cédric Cano <ccano@interfaceconcept.com> Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Cédric Cano authored
agd5f: minor cleanups Signed-off-by:
Cédric Cano <ccano@interfaceconcept.com> Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Marek Olšák authored
The colorbuffer, zbuffer, and texture states are checked only once when they get changed. This improves performance in the apps which emit lots of draw packets and few state changes. This drops performance in glxgears by a 1% or so, but glxgears is not a benchmark we care about. The time spent in the kernel when running Torcs dropped from 33% to 23% and the frame rate is higher, which is a good thing. r600 might need something like this as well. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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