ohci.c 73.5 KB
Newer Older
1
2
/*
 * Driver for OHCI 1394 controllers
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 *
 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

21
#include <linux/compiler.h>
22
#include <linux/delay.h>
Stefan Richter's avatar
Stefan Richter committed
23
#include <linux/device.h>
Andrew Morton's avatar
Andrew Morton committed
24
#include <linux/dma-mapping.h>
25
#include <linux/firewire.h>
Stefan Richter's avatar
Stefan Richter committed
26
#include <linux/firewire-constants.h>
27
#include <linux/gfp.h>
28
29
#include <linux/init.h>
#include <linux/interrupt.h>
Stefan Richter's avatar
Stefan Richter committed
30
#include <linux/io.h>
31
#include <linux/kernel.h>
Stefan Richter's avatar
Stefan Richter committed
32
#include <linux/list.h>
Al Viro's avatar
Al Viro committed
33
#include <linux/mm.h>
34
#include <linux/module.h>
35
#include <linux/moduleparam.h>
36
#include <linux/pci.h>
37
#include <linux/pci_ids.h>
38
#include <linux/spinlock.h>
Stefan Richter's avatar
Stefan Richter committed
39
#include <linux/string.h>
Andrew Morton's avatar
Andrew Morton committed
40

41
#include <asm/atomic.h>
Stefan Richter's avatar
Stefan Richter committed
42
#include <asm/byteorder.h>
43
#include <asm/page.h>
44
#include <asm/system.h>
45

46
47
48
49
#ifdef CONFIG_PPC_PMAC
#include <asm/pmac_feature.h>
#endif

50
51
#include "core.h"
#include "ohci.h"
52

53
54
55
56
57
58
59
60
61
62
63
64
65
#define DESCRIPTOR_OUTPUT_MORE		0
#define DESCRIPTOR_OUTPUT_LAST		(1 << 12)
#define DESCRIPTOR_INPUT_MORE		(2 << 12)
#define DESCRIPTOR_INPUT_LAST		(3 << 12)
#define DESCRIPTOR_STATUS		(1 << 11)
#define DESCRIPTOR_KEY_IMMEDIATE	(2 << 8)
#define DESCRIPTOR_PING			(1 << 7)
#define DESCRIPTOR_YY			(1 << 6)
#define DESCRIPTOR_NO_IRQ		(0 << 4)
#define DESCRIPTOR_IRQ_ERROR		(1 << 4)
#define DESCRIPTOR_IRQ_ALWAYS		(3 << 4)
#define DESCRIPTOR_BRANCH_ALWAYS	(3 << 2)
#define DESCRIPTOR_WAIT			(3 << 0)
66
67
68
69
70
71
72
73
74
75

struct descriptor {
	__le16 req_count;
	__le16 control;
	__le32 data_address;
	__le32 branch_address;
	__le16 res_count;
	__le16 transfer_status;
} __attribute__((aligned(16)));

76
77
78
79
80
81
82
83
84
85
86
87
88
89
struct db_descriptor {
	__le16 first_size;
	__le16 control;
	__le16 second_req_count;
	__le16 first_req_count;
	__le32 branch_address;
	__le16 second_res_count;
	__le16 first_res_count;
	__le32 reserved0;
	__le32 first_buffer;
	__le32 second_buffer;
	__le32 reserved1;
} __attribute__((aligned(16)));

90
91
92
93
#define CONTROL_SET(regs)	(regs)
#define CONTROL_CLEAR(regs)	((regs) + 4)
#define COMMAND_PTR(regs)	((regs) + 12)
#define CONTEXT_MATCH(regs)	((regs) + 16)
94

95
struct ar_buffer {
96
	struct descriptor descriptor;
97
98
99
	struct ar_buffer *next;
	__le32 data[0];
};
100

101
102
103
104
105
struct ar_context {
	struct fw_ohci *ohci;
	struct ar_buffer *current_buffer;
	struct ar_buffer *last_buffer;
	void *pointer;
106
	u32 regs;
107
108
109
	struct tasklet_struct tasklet;
};

110
111
112
113
114
struct context;

typedef int (*descriptor_callback_t)(struct context *ctx,
				     struct descriptor *d,
				     struct descriptor *last);
115
116
117
118
119
120
121
122
123
124
125
126
127

/*
 * A buffer that contains a block of DMA-able coherent memory used for
 * storing a portion of a DMA descriptor program.
 */
struct descriptor_buffer {
	struct list_head list;
	dma_addr_t buffer_bus;
	size_t buffer_size;
	size_t used;
	struct descriptor buffer[0];
};

128
struct context {
Stefan Richter's avatar
Stefan Richter committed
129
	struct fw_ohci *ohci;
130
	u32 regs;
131
	int total_allocation;
Stefan Richter's avatar
Stefan Richter committed
132

133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
	/*
	 * List of page-sized buffers for storing DMA descriptors.
	 * Head of list contains buffers in use and tail of list contains
	 * free buffers.
	 */
	struct list_head buffer_list;

	/*
	 * Pointer to a buffer inside buffer_list that contains the tail
	 * end of the current DMA program.
	 */
	struct descriptor_buffer *buffer_tail;

	/*
	 * The descriptor containing the branch address of the first
	 * descriptor that has not yet been filled by the device.
	 */
	struct descriptor *last;

	/*
	 * The last descriptor in the DMA program.  It contains the branch
	 * address that must be updated upon appending a new descriptor.
	 */
	struct descriptor *prev;
157
158
159

	descriptor_callback_t callback;

Stefan Richter's avatar
Stefan Richter committed
160
	struct tasklet_struct tasklet;
161
162
};

163
164
165
166
167
168
#define IT_HEADER_SY(v)          ((v) <<  0)
#define IT_HEADER_TCODE(v)       ((v) <<  4)
#define IT_HEADER_CHANNEL(v)     ((v) <<  8)
#define IT_HEADER_TAG(v)         ((v) << 14)
#define IT_HEADER_SPEED(v)       ((v) << 16)
#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170
171

struct iso_context {
	struct fw_iso_context base;
172
	struct context context;
173
	int excess_bytes;
174
175
	void *header;
	size_t header_length;
176
177
178
179
180
181
182
183
184
185
186
};

#define CONFIG_ROM_SIZE 1024

struct fw_ohci {
	struct fw_card card;

	__iomem char *registers;
	dma_addr_t self_id_bus;
	__le32 *self_id_cpu;
	struct tasklet_struct bus_reset_tasklet;
187
	int node_id;
188
	int generation;
189
	int request_generation;	/* for timestamping incoming requests */
190
	atomic_t bus_seconds;
191
192

	bool use_dualbuffer;
193
	bool old_uninorth;
194
	bool bus_reset_packet_quirk;
195

196
197
198
199
	/*
	 * Spinlock for accessing fw_ohci data.  Never call out of
	 * this driver with this lock held.
	 */
200
201
202
203
204
205
206
207
208
209
210
211
	spinlock_t lock;
	u32 self_id_buffer[512];

	/* Config rom buffers */
	__be32 *config_rom;
	dma_addr_t config_rom_bus;
	__be32 *next_config_rom;
	dma_addr_t next_config_rom_bus;
	u32 next_header;

	struct ar_context ar_request_ctx;
	struct ar_context ar_response_ctx;
212
213
	struct context at_request_ctx;
	struct context at_response_ctx;
214
215
216

	u32 it_context_mask;
	struct iso_context *it_context_list;
217
	u64 ir_context_channels;
218
219
220
221
	u32 ir_context_mask;
	struct iso_context *ir_context_list;
};

Adrian Bunk's avatar
Adrian Bunk committed
222
static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223
224
225
226
{
	return container_of(card, struct fw_ohci, card);
}

227
228
229
230
231
232
#define IT_CONTEXT_CYCLE_MATCH_ENABLE	0x80000000
#define IR_CONTEXT_BUFFER_FILL		0x80000000
#define IR_CONTEXT_ISOCH_HEADER		0x40000000
#define IR_CONTEXT_CYCLE_MATCH_ENABLE	0x20000000
#define IR_CONTEXT_MULTI_CHANNEL_MODE	0x10000000
#define IR_CONTEXT_DUAL_BUFFER_MODE	0x08000000
233
234
235
236
237
238

#define CONTEXT_RUN	0x8000
#define CONTEXT_WAKE	0x1000
#define CONTEXT_DEAD	0x0800
#define CONTEXT_ACTIVE	0x0400

239
#define OHCI1394_MAX_AT_REQ_RETRIES	0xf
240
241
242
243
244
245
246
#define OHCI1394_MAX_AT_RESP_RETRIES	0x2
#define OHCI1394_MAX_PHYS_RESP_RETRIES	0x8

#define OHCI1394_REGISTER_SIZE		0x800
#define OHCI_LOOP_COUNT			500
#define OHCI1394_PCI_HCI_Control	0x40
#define SELF_ID_BUF_SIZE		0x800
247
#define OHCI_TCODE_PHY_PACKET		0x0e
248
#define OHCI_VERSION_1_1		0x010010
249

250
251
static char ohci_driver_name[] = KBUILD_MODNAME;

252
253
#ifdef CONFIG_FIREWIRE_OHCI_DEBUG

254
#define OHCI_PARAM_DEBUG_AT_AR		1
255
#define OHCI_PARAM_DEBUG_SELFIDS	2
256
257
#define OHCI_PARAM_DEBUG_IRQS		4
#define OHCI_PARAM_DEBUG_BUSRESETS	8 /* only effective before chip init */
258
259
260
261
262

static int param_debug;
module_param_named(debug, param_debug, int, 0644);
MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
	", AT/AR events = "	__stringify(OHCI_PARAM_DEBUG_AT_AR)
263
264
265
	", self-IDs = "		__stringify(OHCI_PARAM_DEBUG_SELFIDS)
	", IRQs = "		__stringify(OHCI_PARAM_DEBUG_IRQS)
	", busReset events = "	__stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266
267
268
269
	", or a combination, or all = -1)");

static void log_irqs(u32 evt)
{
270
271
272
273
274
275
	if (likely(!(param_debug &
			(OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
		return;

	if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
	    !(evt & OHCI1394_busReset))
276
277
		return;

278
	fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279
280
281
282
283
284
285
286
287
288
	    evt & OHCI1394_selfIDComplete	? " selfID"		: "",
	    evt & OHCI1394_RQPkt		? " AR_req"		: "",
	    evt & OHCI1394_RSPkt		? " AR_resp"		: "",
	    evt & OHCI1394_reqTxComplete	? " AT_req"		: "",
	    evt & OHCI1394_respTxComplete	? " AT_resp"		: "",
	    evt & OHCI1394_isochRx		? " IR"			: "",
	    evt & OHCI1394_isochTx		? " IT"			: "",
	    evt & OHCI1394_postedWriteErr	? " postedWriteErr"	: "",
	    evt & OHCI1394_cycleTooLong		? " cycleTooLong"	: "",
	    evt & OHCI1394_cycle64Seconds	? " cycle64Seconds"	: "",
289
	    evt & OHCI1394_cycleInconsistent	? " cycleInconsistent"	: "",
290
291
292
293
294
295
296
	    evt & OHCI1394_regAccessFail	? " regAccessFail"	: "",
	    evt & OHCI1394_busReset		? " busReset"		: "",
	    evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
		    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
		    OHCI1394_respTxComplete | OHCI1394_isochRx |
		    OHCI1394_isochTx | OHCI1394_postedWriteErr |
		    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
297
		    OHCI1394_cycleInconsistent |
298
		    OHCI1394_regAccessFail | OHCI1394_busReset)
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
						? " ?"			: "");
}

static const char *speed[] = {
	[0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
};
static const char *power[] = {
	[0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
	[4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
};
static const char port[] = { '.', '-', 'p', 'c', };

static char _p(u32 *s, int shift)
{
	return port[*s >> shift & 3];
}

316
static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
317
318
319
320
{
	if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
		return;

321
322
	fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
		  self_id_count, generation, node_id);
323
324
325

	for (; self_id_count--; ++s)
		if ((*s & 1 << 23) == 0)
326
327
328
329
330
331
			fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
			    "%s gc=%d %s %s%s%s\n",
			    *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
			    speed[*s >> 14 & 3], *s >> 16 & 63,
			    power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
			    *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
332
		else
333
334
335
336
			fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
			    *s, *s >> 24 & 63,
			    _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
			    _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
}

static const char *evts[] = {
	[0x00] = "evt_no_status",	[0x01] = "-reserved-",
	[0x02] = "evt_long_packet",	[0x03] = "evt_missing_ack",
	[0x04] = "evt_underrun",	[0x05] = "evt_overrun",
	[0x06] = "evt_descriptor_read",	[0x07] = "evt_data_read",
	[0x08] = "evt_data_write",	[0x09] = "evt_bus_reset",
	[0x0a] = "evt_timeout",		[0x0b] = "evt_tcode_err",
	[0x0c] = "-reserved-",		[0x0d] = "-reserved-",
	[0x0e] = "evt_unknown",		[0x0f] = "evt_flushed",
	[0x10] = "-reserved-",		[0x11] = "ack_complete",
	[0x12] = "ack_pending ",	[0x13] = "-reserved-",
	[0x14] = "ack_busy_X",		[0x15] = "ack_busy_A",
	[0x16] = "ack_busy_B",		[0x17] = "-reserved-",
	[0x18] = "-reserved-",		[0x19] = "-reserved-",
	[0x1a] = "-reserved-",		[0x1b] = "ack_tardy",
	[0x1c] = "-reserved-",		[0x1d] = "ack_data_error",
	[0x1e] = "ack_type_error",	[0x1f] = "-reserved-",
	[0x20] = "pending/cancelled",
};
static const char *tcodes[] = {
	[0x0] = "QW req",		[0x1] = "BW req",
	[0x2] = "W resp",		[0x3] = "-reserved-",
	[0x4] = "QR req",		[0x5] = "BR req",
	[0x6] = "QR resp",		[0x7] = "BR resp",
	[0x8] = "cycle start",		[0x9] = "Lk req",
	[0xa] = "async stream packet",	[0xb] = "Lk resp",
	[0xc] = "-reserved-",		[0xd] = "-reserved-",
	[0xe] = "link internal",	[0xf] = "-reserved-",
};
static const char *phys[] = {
	[0x0] = "phy config packet",	[0x1] = "link-on packet",
	[0x2] = "self-id packet",	[0x3] = "-reserved-",
};

static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
{
	int tcode = header[0] >> 4 & 0xf;
	char specific[12];

	if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
		return;

	if (unlikely(evt >= ARRAY_SIZE(evts)))
			evt = 0x1f;

384
	if (evt == OHCI1394_evt_bus_reset) {
385
386
		fw_notify("A%c evt_bus_reset, generation %d\n",
		    dir, (header[2] >> 16) & 0xff);
387
388
389
		return;
	}

390
	if (header[0] == ~header[1]) {
391
392
		fw_notify("A%c %s, %s, %08x\n",
		    dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
		return;
	}

	switch (tcode) {
	case 0x0: case 0x6: case 0x8:
		snprintf(specific, sizeof(specific), " = %08x",
			 be32_to_cpu((__force __be32)header[3]));
		break;
	case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
		snprintf(specific, sizeof(specific), " %x,%x",
			 header[3] >> 16, header[3] & 0xffff);
		break;
	default:
		specific[0] = '\0';
	}

	switch (tcode) {
	case 0xe: case 0xa:
411
		fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
412
413
		break;
	case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414
415
416
417
418
419
		fw_notify("A%c spd %x tl %02x, "
		    "%04x -> %04x, %s, "
		    "%s, %04x%08x%s\n",
		    dir, speed, header[0] >> 10 & 0x3f,
		    header[1] >> 16, header[0] >> 16, evts[evt],
		    tcodes[tcode], header[1] & 0xffff, header[2], specific);
420
421
		break;
	default:
422
423
424
425
426
427
		fw_notify("A%c spd %x tl %02x, "
		    "%04x -> %04x, %s, "
		    "%s%s\n",
		    dir, speed, header[0] >> 10 & 0x3f,
		    header[1] >> 16, header[0] >> 16, evts[evt],
		    tcodes[tcode], specific);
428
429
430
431
432
433
	}
}

#else

#define log_irqs(evt)
434
#define log_selfids(node_id, generation, self_id_count, sid)
435
436
437
438
#define log_ar_at_event(dir, speed, header, evt)

#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */

Adrian Bunk's avatar
Adrian Bunk committed
439
static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
440
441
442
443
{
	writel(data, ohci->registers + offset);
}

Adrian Bunk's avatar
Adrian Bunk committed
444
static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
445
446
447
448
{
	return readl(ohci->registers + offset);
}

Adrian Bunk's avatar
Adrian Bunk committed
449
static inline void flush_writes(const struct fw_ohci *ohci)
450
451
452
453
454
{
	/* Do a dummy read to flush writes. */
	reg_read(ohci, OHCI1394_Version);
}

455
456
static int ohci_update_phy_reg(struct fw_card *card, int addr,
			       int clear_bits, int set_bits)
457
458
459
460
461
{
	struct fw_ohci *ohci = fw_ohci(card);
	u32 val, old;

	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
462
	flush_writes(ohci);
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
	msleep(2);
	val = reg_read(ohci, OHCI1394_PhyControl);
	if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
		fw_error("failed to set phy reg bits.\n");
		return -EBUSY;
	}

	old = OHCI1394_PhyControl_ReadData(val);
	old = (old & ~clear_bits) | set_bits;
	reg_write(ohci, OHCI1394_PhyControl,
		  OHCI1394_PhyControl_Write(addr, old));

	return 0;
}

478
static int ar_context_add_page(struct ar_context *ctx)
479
{
480
481
	struct device *dev = ctx->ohci->card.device;
	struct ar_buffer *ab;
482
	dma_addr_t uninitialized_var(ab_bus);
483
484
	size_t offset;

485
	ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
486
487
488
	if (ab == NULL)
		return -ENOMEM;

489
	ab->next = NULL;
490
	memset(&ab->descriptor, 0, sizeof(ab->descriptor));
491
492
493
	ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
						    DESCRIPTOR_STATUS |
						    DESCRIPTOR_BRANCH_ALWAYS);
494
495
496
497
498
499
	offset = offsetof(struct ar_buffer, data);
	ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
	ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
	ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
	ab->descriptor.branch_address = 0;

500
	ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
501
502
503
	ctx->last_buffer->next = ab;
	ctx->last_buffer = ab;

504
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
505
	flush_writes(ctx->ohci);
506
507

	return 0;
508
509
}

510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
static void ar_context_release(struct ar_context *ctx)
{
	struct ar_buffer *ab, *ab_next;
	size_t offset;
	dma_addr_t ab_bus;

	for (ab = ctx->current_buffer; ab; ab = ab_next) {
		ab_next = ab->next;
		offset = offsetof(struct ar_buffer, data);
		ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
		dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
				  ab, ab_bus);
	}
}

525
526
527
528
529
530
531
#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
#define cond_le32_to_cpu(v) \
	(ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
#else
#define cond_le32_to_cpu(v) le32_to_cpu(v)
#endif

532
static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
533
534
{
	struct fw_ohci *ohci = ctx->ohci;
535
536
	struct fw_packet p;
	u32 status, length, tcode;
537
	int evt;
538

539
540
541
	p.header[0] = cond_le32_to_cpu(buffer[0]);
	p.header[1] = cond_le32_to_cpu(buffer[1]);
	p.header[2] = cond_le32_to_cpu(buffer[2]);
542
543
544
545
546

	tcode = (p.header[0] >> 4) & 0x0f;
	switch (tcode) {
	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
547
		p.header[3] = (__force __u32) buffer[3];
548
		p.header_length = 16;
549
		p.payload_length = 0;
550
551
552
		break;

	case TCODE_READ_BLOCK_REQUEST :
553
		p.header[3] = cond_le32_to_cpu(buffer[3]);
554
555
556
557
558
		p.header_length = 16;
		p.payload_length = 0;
		break;

	case TCODE_WRITE_BLOCK_REQUEST:
559
560
561
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
562
		p.header[3] = cond_le32_to_cpu(buffer[3]);
563
		p.header_length = 16;
564
		p.payload_length = p.header[3] >> 16;
565
566
567
568
		break;

	case TCODE_WRITE_RESPONSE:
	case TCODE_READ_QUADLET_REQUEST:
569
	case OHCI_TCODE_PHY_PACKET:
570
		p.header_length = 12;
571
		p.payload_length = 0;
572
		break;
573
574
575
576
577

	default:
		/* FIXME: Stop context, discard everything, and restart? */
		p.header_length = 0;
		p.payload_length = 0;
578
	}
579

580
581
582
583
	p.payload = (void *) buffer + p.header_length;

	/* FIXME: What to do about evt_* errors? */
	length = (p.header_length + p.payload_length + 3) / 4;
584
	status = cond_le32_to_cpu(buffer[length]);
585
	evt    = (status >> 16) & 0x1f;
586

587
	p.ack        = evt - 16;
588
589
590
	p.speed      = (status >> 21) & 0x7;
	p.timestamp  = status & 0xffff;
	p.generation = ohci->request_generation;
591

592
	log_ar_at_event('R', p.speed, p.header, evt);
593

594
595
	/*
	 * The OHCI bus reset handler synthesizes a phy packet with
596
597
598
599
600
	 * the new generation number when a bus reset happens (see
	 * section 8.4.2.3).  This helps us determine when a request
	 * was received and make sure we send the response in the same
	 * generation.  We only need this for requests; for responses
	 * we use the unique tlabel for finding the matching
601
	 * request.
602
603
604
605
	 *
	 * Alas some chips sometimes emit bus reset packets with a
	 * wrong generation.  We set the correct generation for these
	 * at a slightly incorrect time (in bus_reset_tasklet).
606
	 */
607
608
609
610
	if (evt == OHCI1394_evt_bus_reset) {
		if (!ohci->bus_reset_packet_quirk)
			ohci->request_generation = (p.header[2] >> 16) & 0xff;
	} else if (ctx == &ohci->ar_request_ctx) {
611
		fw_core_handle_request(&ohci->card, &p);
612
	} else {
613
		fw_core_handle_response(&ohci->card, &p);
614
	}
615

616
617
	return buffer + length + 1;
}
618

619
620
621
622
623
624
625
626
627
628
629
630
631
static void ar_context_tasklet(unsigned long data)
{
	struct ar_context *ctx = (struct ar_context *)data;
	struct fw_ohci *ohci = ctx->ohci;
	struct ar_buffer *ab;
	struct descriptor *d;
	void *buffer, *end;

	ab = ctx->current_buffer;
	d = &ab->descriptor;

	if (d->res_count == 0) {
		size_t size, rest, offset;
632
633
		dma_addr_t start_bus;
		void *start;
634

635
636
		/*
		 * This descriptor is finished and we may have a
637
		 * packet split across this and the next buffer. We
638
639
		 * reuse the page for reassembling the split packet.
		 */
640
641

		offset = offsetof(struct ar_buffer, data);
642
643
		start = buffer = ab;
		start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
644
645
646
647
648
649
650
651
652
653
654
655
656
657

		ab = ab->next;
		d = &ab->descriptor;
		size = buffer + PAGE_SIZE - ctx->pointer;
		rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
		memmove(buffer, ctx->pointer, size);
		memcpy(buffer + size, ab->data, rest);
		ctx->current_buffer = ab;
		ctx->pointer = (void *) ab->data + rest;
		end = buffer + size + rest;

		while (buffer < end)
			buffer = handle_ar_packet(ctx, buffer);

658
		dma_free_coherent(ohci->card.device, PAGE_SIZE,
659
				  start, start_bus);
660
661
662
663
664
665
666
667
668
		ar_context_add_page(ctx);
	} else {
		buffer = ctx->pointer;
		ctx->pointer = end =
			(void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);

		while (buffer < end)
			buffer = handle_ar_packet(ctx, buffer);
	}
669
670
}

671
672
static int ar_context_init(struct ar_context *ctx,
			   struct fw_ohci *ohci, u32 regs)
673
{
674
	struct ar_buffer ab;
675

676
677
678
	ctx->regs        = regs;
	ctx->ohci        = ohci;
	ctx->last_buffer = &ab;
679
680
	tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);

681
682
683
684
685
	ar_context_add_page(ctx);
	ar_context_add_page(ctx);
	ctx->current_buffer = ab.next;
	ctx->pointer = ctx->current_buffer->data;

686
687
688
689
690
691
692
693
694
695
	return 0;
}

static void ar_context_run(struct ar_context *ctx)
{
	struct ar_buffer *ab = ctx->current_buffer;
	dma_addr_t ab_bus;
	size_t offset;

	offset = offsetof(struct ar_buffer, data);
696
	ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
697
698

	reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
699
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
700
	flush_writes(ctx->ohci);
701
}
Stefan Richter's avatar
Stefan Richter committed
702

703
static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
704
705
706
707
708
709
710
711
712
713
714
715
716
{
	int b, key;

	b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
	key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;

	/* figure out which descriptor the branch address goes in */
	if (z == 2 && (b == 3 || key == 2))
		return d;
	else
		return d + z - 1;
}

717
718
719
720
721
722
static void context_tasklet(unsigned long data)
{
	struct context *ctx = (struct context *) data;
	struct descriptor *d, *last;
	u32 address;
	int z;
723
	struct descriptor_buffer *desc;
724

725
726
727
	desc = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);
	last = ctx->last;
728
	while (last->branch_address != 0) {
729
		struct descriptor_buffer *old_desc = desc;
730
731
		address = le32_to_cpu(last->branch_address);
		z = address & 0xf;
732
733
734
735
736
737
738
739
740
		address &= ~0xf;

		/* If the branch address points to a buffer outside of the
		 * current buffer, advance to the next buffer. */
		if (address < desc->buffer_bus ||
				address >= desc->buffer_bus + desc->used)
			desc = list_entry(desc->list.next,
					struct descriptor_buffer, list);
		d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
741
		last = find_branch_descriptor(d, z);
742
743
744
745

		if (!ctx->callback(ctx, d, last))
			break;

746
747
748
749
750
751
752
753
754
755
		if (old_desc != desc) {
			/* If we've advanced to the next buffer, move the
			 * previous buffer to the free list. */
			unsigned long flags;
			old_desc->used = 0;
			spin_lock_irqsave(&ctx->ohci->lock, flags);
			list_move_tail(&old_desc->list, &ctx->buffer_list);
			spin_unlock_irqrestore(&ctx->ohci->lock, flags);
		}
		ctx->last = last;
756
757
758
	}
}

759
760
761
762
/*
 * Allocate a new buffer and add it to the list of free buffers for this
 * context.  Must be called with ohci->lock held.
 */
763
static int context_add_buffer(struct context *ctx)
764
765
{
	struct descriptor_buffer *desc;
766
	dma_addr_t uninitialized_var(bus_addr);
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
	int offset;

	/*
	 * 16MB of descriptors should be far more than enough for any DMA
	 * program.  This will catch run-away userspace or DoS attacks.
	 */
	if (ctx->total_allocation >= 16*1024*1024)
		return -ENOMEM;

	desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
			&bus_addr, GFP_ATOMIC);
	if (!desc)
		return -ENOMEM;

	offset = (void *)&desc->buffer - (void *)desc;
	desc->buffer_size = PAGE_SIZE - offset;
	desc->buffer_bus = bus_addr + offset;
	desc->used = 0;

	list_add_tail(&desc->list, &ctx->buffer_list);
	ctx->total_allocation += PAGE_SIZE;

	return 0;
}

792
793
static int context_init(struct context *ctx, struct fw_ohci *ohci,
			u32 regs, descriptor_callback_t callback)
794
795
796
{
	ctx->ohci = ohci;
	ctx->regs = regs;
797
798
799
800
	ctx->total_allocation = 0;

	INIT_LIST_HEAD(&ctx->buffer_list);
	if (context_add_buffer(ctx) < 0)
801
802
		return -ENOMEM;

803
804
805
	ctx->buffer_tail = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);

806
807
808
	tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
	ctx->callback = callback;

809
810
	/*
	 * We put a dummy descriptor in the buffer that has a NULL
811
	 * branch address and looks like it's been sent.  That way we
812
	 * have a descriptor to append DMA programs to.
813
	 */
814
815
816
817
818
819
	memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
	ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
	ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
	ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
	ctx->last = ctx->buffer_tail->buffer;
	ctx->prev = ctx->buffer_tail->buffer;
820
821
822
823

	return 0;
}

824
static void context_release(struct context *ctx)
825
826
{
	struct fw_card *card = &ctx->ohci->card;
827
	struct descriptor_buffer *desc, *tmp;
828

829
830
831
832
	list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
		dma_free_coherent(card->device, PAGE_SIZE, desc,
			desc->buffer_bus -
			((void *)&desc->buffer - (void *)desc));
833
834
}

835
/* Must be called with ohci->lock held */
836
837
static struct descriptor *context_get_descriptors(struct context *ctx,
						  int z, dma_addr_t *d_bus)
838
{
839
840
841
842
843
844
845
846
847
	struct descriptor *d = NULL;
	struct descriptor_buffer *desc = ctx->buffer_tail;

	if (z * sizeof(*d) > desc->buffer_size)
		return NULL;

	if (z * sizeof(*d) > desc->buffer_size - desc->used) {
		/* No room for the descriptor in this buffer, so advance to the
		 * next one. */
848

849
850
851
852
853
854
855
856
857
858
		if (desc->list.next == &ctx->buffer_list) {
			/* If there is no free buffer next in the list,
			 * allocate one. */
			if (context_add_buffer(ctx) < 0)
				return NULL;
		}
		desc = list_entry(desc->list.next,
				struct descriptor_buffer, list);
		ctx->buffer_tail = desc;
	}
859

860
	d = desc->buffer + desc->used / sizeof(*d);
861
	memset(d, 0, z * sizeof(*d));
862
	*d_bus = desc->buffer_bus + desc->used;
863
864
865
866

	return d;
}

867
static void context_run(struct context *ctx, u32 extra)
868
869
870
{
	struct fw_ohci *ohci = ctx->ohci;

871
	reg_write(ohci, COMMAND_PTR(ctx->regs),
872
		  le32_to_cpu(ctx->last->branch_address));
873
874
	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
875
876
877
878
879
880
881
	flush_writes(ohci);
}

static void context_append(struct context *ctx,
			   struct descriptor *d, int z, int extra)
{
	dma_addr_t d_bus;
882
	struct descriptor_buffer *desc = ctx->buffer_tail;
883

884
	d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
885

886
887
888
	desc->used += (z + extra) * sizeof(*d);
	ctx->prev->branch_address = cpu_to_le32(d_bus | z);
	ctx->prev = find_branch_descriptor(d, z);
889

890
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
891
892
893
894
895
896
	flush_writes(ctx->ohci);
}

static void context_stop(struct context *ctx)
{
	u32 reg;
897
	int i;
898

899
	reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
900
	flush_writes(ctx->ohci);
901

902
	for (i = 0; i < 10; i++) {
903
		reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
904
		if ((reg & CONTEXT_ACTIVE) == 0)
905
			return;
906

907
		mdelay(1);
908
	}
909
	fw_error("Error: DMA context still active (0x%08x)\n", reg);
910
}
911

912
913
914
struct driver_data {
	struct fw_packet *packet;
};
915

916
917
/*
 * This function apppends a packet to the DMA queue for transmission.
918
 * Must always be called with the ochi->lock held to ensure proper
919
920
 * generation handling and locking around packet queue manipulation.
 */
921
922
static int at_context_queue_packet(struct context *ctx,
				   struct fw_packet *packet)
923
924
{
	struct fw_ohci *ohci = ctx->ohci;
925
	dma_addr_t d_bus, uninitialized_var(payload_bus);
926
927
928
	struct driver_data *driver_data;
	struct descriptor *d, *last;
	__le32 *header;
929
	int z, tcode;
930
	u32 reg;
931

932
933
934
935
	d = context_get_descriptors(ctx, 4, &d_bus);
	if (d == NULL) {
		packet->ack = RCODE_SEND_ERROR;
		return -1;
936
937
	}

938
	d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
939
940
	d[0].res_count = cpu_to_le16(packet->timestamp);

941
942
	/*
	 * The DMA format for asyncronous link packets is different
943
944
	 * from the IEEE1394 layout, so shift the fields around
	 * accordingly.  If header_length is 8, it's a PHY packet, to
945
946
	 * which we need to prepend an extra quadlet.
	 */
947
948

	header = (__le32 *) &d[1];
949
950
951
	switch (packet->header_length) {
	case 16:
	case 12:
952
953
954
955
956
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
					(packet->header[0] & 0xffff0000));
		header[2] = cpu_to_le32(packet->header[2]);
957
958
959

		tcode = (packet->header[0] >> 4) & 0x0f;
		if (TCODE_IS_BLOCK_PACKET(tcode))
960
			header[3] = cpu_to_le32(packet->header[3]);
961
		else
962
963
964
			header[3] = (__force __le32) packet->header[3];

		d[0].req_count = cpu_to_le16(packet->header_length);
965
966
967
		break;

	case 8:
968
969
970
971
972
		header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
					(packet->speed << 16));
		header[1] = cpu_to_le32(packet->header[0]);
		header[2] = cpu_to_le32(packet->header[1]);
		d[0].req_count = cpu_to_le16(12);
973
974
975
976
977
978
979
980
981
982
983
984
985
		break;

	case 4:
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
		d[0].req_count = cpu_to_le16(8);
		break;

	default:
		/* BUG(); */
		packet->ack = RCODE_SEND_ERROR;
		return -1;
986
987
	}

988
989
	driver_data = (struct driver_data *) &d[3];
	driver_data->packet = packet;
990
	packet->driver_data = driver_data;
991

992
993
994
995
	if (packet->payload_length > 0) {
		payload_bus =
			dma_map_single(ohci->card.device, packet->payload,
				       packet->payload_length, DMA_TO_DEVICE);
996
		if (dma_mapping_error(ohci->card.device, payload_bus)) {
997
998
999
			packet->ack = RCODE_SEND_ERROR;
			return -1;
		}
1000
		packet->payload_bus = payload_bus;
1001
1002
1003
1004
1005

		d[2].req_count    = cpu_to_le16(packet->payload_length);
		d[2].data_address = cpu_to_le32(payload_bus);
		last = &d[2];
		z = 3;
1006
	} else {
1007
1008
		last = &d[0];
		z = 2;
1009
1010
	}

1011
1012
1013
	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
				     DESCRIPTOR_IRQ_ALWAYS |
				     DESCRIPTOR_BRANCH_ALWAYS);
1014

1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
	/*
	 * If the controller and packet generations don't match, we need to
	 * bail out and try again.  If IntEvent.busReset is set, the AT context
	 * is halted, so appending to the context and trying to run it is
	 * futile.  Most controllers do the right thing and just flush the AT
	 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
	 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
	 * up stalling out.  So we just bail out in software and try again
	 * later, and everyone is happy.
	 * FIXME: Document how the locking works.
	 */
	if (ohci->generation != packet->generation ||
	    reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1028
1029
1030
		if (packet->payload_length > 0)
			dma_unmap_single(ohci->card.device, payload_bus,
					 packet->payload_length, DMA_TO_DEVICE);
1031
1032
1033
1034
1035
		packet->ack = RCODE_GENERATION;
		return -1;
	}

	context_append(ctx, d, z, 4 - z);
1036

1037
	/* If the context isn't already running, start it up. */
1038
	reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1039
	if ((reg & CONTEXT_RUN) == 0)
1040
1041
1042
		context_run(ctx, 0);

	return 0;
1043
1044
}

1045
1046
1047
static int handle_at_packet(struct context *context,
			    struct descriptor *d,
			    struct descriptor *last)
1048
{
1049
	struct driver_data *driver_data;
1050
	struct fw_packet *packet;
1051
	struct fw_ohci *ohci = context->ohci;
1052
1053
	int evt;

1054
1055
1056
	if (last->transfer_status == 0)
		/* This descriptor isn't done yet, stop iteration. */
		return 0;
1057

1058
1059
1060
1061
1062
	driver_data = (struct driver_data *) &d[3];
	packet = driver_data->packet;
	if (packet == NULL)
		/* This packet was cancelled, just continue. */
		return 1;
1063

1064
1065
	if (packet->payload_bus)
		dma_unmap_single(ohci->card.device, packet->payload_bus,
1066
1067
				 packet->payload_length, DMA_TO_DEVICE);

1068
1069
	evt = le16_to_cpu(last->transfer_status) & 0x1f;
	packet->timestamp = le16_to_cpu(last->res_count);
1070

1071
1072
	log_ar_at_event('T', packet->speed, packet->header, evt);

1073
1074
1075
1076
1077
	switch (evt) {
	case OHCI1394_evt_timeout:
		/* Async response transmit timed out. */
		packet->ack = RCODE_CANCELLED;
		break;
1078

1079
	case OHCI1394_evt_flushed:
1080
1081
1082
1083
		/*
		 * The packet was flushed should give same error as
		 * when we try to use a stale generation count.
		 */
1084
1085
		packet->ack = RCODE_GENERATION;
		break;
1086

1087
	case OHCI1394_evt_missing_ack:
1088
1089
1090
1091
		/*
		 * Using a valid (current) generation count, but the
		 * node is not on the bus or not sending acks.
		 */
1092
1093
		packet->ack = RCODE_NO_ACK;
		break;
1094

1095
1096
1097
1098
1099
1100
1101
1102
1103
	case ACK_COMPLETE + 0x10:
	case ACK_PENDING + 0x10:
	case ACK_BUSY_X + 0x10:
	case ACK_BUSY_A + 0x10:
	case ACK_BUSY_B + 0x10:
	case ACK_DATA_ERROR + 0x10:
	case ACK_TYPE_ERROR + 0x10:
		packet->ack = evt - 0x10;
		break;
1104

1105
1106
1107
1108
	default:
		packet->ack = RCODE_SEND_ERROR;
		break;
	}
1109

1110
	packet->callback(packet, &ohci->card, packet->ack);
1111

1112
	return 1;
1113
1114
}

1115
1116
1117
1118
1119
#define HEADER_GET_DESTINATION(q)	(((q) >> 16) & 0xffff)
#define HEADER_GET_TCODE(q)		(((q) >> 4) & 0x0f)
#define HEADER_GET_OFFSET_HIGH(q)	(((q) >> 0) & 0xffff)
#define HEADER_GET_DATA_LENGTH(q)	(((q) >> 16) & 0xffff)
#define HEADER_GET_EXTENDED_TCODE(q)	(((q) >> 0) & 0xffff)
1120

1121
1122
static void handle_local_rom(struct fw_ohci *ohci,
			     struct fw_packet *packet, u32 csr)
1123
1124
1125
1126
{
	struct fw_packet response;
	int tcode, length, i;

1127
	tcode = HEADER_GET_TCODE(packet->header[0]);
1128
	if (TCODE_IS_BLOCK_PACKET(tcode))
1129
		length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
	else
		length = 4;

	i = csr - CSR_CONFIG_ROM;
	if (i + length > CONFIG_ROM_SIZE) {
		fw_fill_response(&response, packet->header,
				 RCODE_ADDRESS_ERROR, NULL, 0);
	} else if (!TCODE_IS_READ_REQUEST(tcode)) {
		fw_fill_response(&response, packet->header,
				 RCODE_TYPE_ERROR, NULL, 0);
	} else {
		fw_fill_response(&response, packet->header, RCODE_COMPLETE,
				 (void *) ohci->config_rom + i, length);
	}

	fw_core_handle_response(&ohci->card, &response);
}

1148
1149
static void handle_local_lock(struct fw_ohci *ohci,
			      struct fw_packet *packet, u32 csr)
1150
1151
1152
1153
1154
1155
{
	struct fw_packet response;
	int tcode, length, ext_tcode, sel;
	__be32 *payload, lock_old;
	u32 lock_arg, lock_data;

1156
1157
	tcode = HEADER_GET_TCODE(packet->header[0]);
	length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1158
	payload = packet->payload;
1159
	ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170