amdgpu_cs.c 29.3 KB
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/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
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#include <linux/pagemap.h>
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#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"

int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
		       u32 ip_instance, u32 ring,
		       struct amdgpu_ring **out_ring)
{
	/* Right now all IPs have only one instance - multiple rings. */
	if (ip_instance != 0) {
		DRM_ERROR("invalid ip instance: %d\n", ip_instance);
		return -EINVAL;
	}

	switch (ip_type) {
	default:
		DRM_ERROR("unknown ip type: %d\n", ip_type);
		return -EINVAL;
	case AMDGPU_HW_IP_GFX:
		if (ring < adev->gfx.num_gfx_rings) {
			*out_ring = &adev->gfx.gfx_ring[ring];
		} else {
			DRM_ERROR("only %d gfx rings are supported now\n",
				  adev->gfx.num_gfx_rings);
			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_COMPUTE:
		if (ring < adev->gfx.num_compute_rings) {
			*out_ring = &adev->gfx.compute_ring[ring];
		} else {
			DRM_ERROR("only %d compute rings are supported now\n",
				  adev->gfx.num_compute_rings);
			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_DMA:
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		if (ring < adev->sdma.num_instances) {
			*out_ring = &adev->sdma.instance[ring].ring;
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		} else {
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			DRM_ERROR("only %d SDMA rings are supported\n",
				  adev->sdma.num_instances);
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			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_UVD:
		*out_ring = &adev->uvd.ring;
		break;
	case AMDGPU_HW_IP_VCE:
		if (ring < 2){
			*out_ring = &adev->vce.ring[ring];
		} else {
			DRM_ERROR("only two VCE rings are supported\n");
			return -EINVAL;
		}
		break;
	}
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	if (!(*out_ring && (*out_ring)->adev)) {
		DRM_ERROR("Ring %d is not initialized on IP %d\n",
			  ring, ip_type);
		return -EINVAL;
	}

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	return 0;
}

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static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
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				      struct drm_amdgpu_cs_chunk_fence *data,
				      uint32_t *offset)
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{
	struct drm_gem_object *gobj;
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	unsigned long size;
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	gobj = drm_gem_object_lookup(p->filp, data->handle);
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	if (gobj == NULL)
		return -EINVAL;

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	p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
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	p->uf_entry.priority = 0;
	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
	p->uf_entry.tv.shared = true;
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	p->uf_entry.user_pages = NULL;
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	size = amdgpu_bo_size(p->uf_entry.robj);
	if (size != PAGE_SIZE || (data->offset + 8) > size)
		return -EINVAL;

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	*offset = data->offset;
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	drm_gem_object_unreference_unlocked(gobj);
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	if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
		amdgpu_bo_unref(&p->uf_entry.robj);
		return -EINVAL;
	}

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	return 0;
}

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int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
{
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	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_vm *vm = &fpriv->vm;
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	union drm_amdgpu_cs *cs = data;
	uint64_t *chunk_array_user;
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	uint64_t *chunk_array;
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	unsigned size, num_ibs = 0;
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	uint32_t uf_offset = 0;
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	int i;
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	int ret;
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	if (cs->in.num_chunks == 0)
		return 0;

	chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (!chunk_array)
		return -ENOMEM;
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	p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
	if (!p->ctx) {
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		ret = -EINVAL;
		goto free_chunk;
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	}
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	/* get chunks */
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	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
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	if (copy_from_user(chunk_array, chunk_array_user,
			   sizeof(uint64_t)*cs->in.num_chunks)) {
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		ret = -EFAULT;
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		goto put_ctx;
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	}

	p->nchunks = cs->in.num_chunks;
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	p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
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			    GFP_KERNEL);
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	if (!p->chunks) {
		ret = -ENOMEM;
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		goto put_ctx;
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	}

	for (i = 0; i < p->nchunks; i++) {
		struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
		struct drm_amdgpu_cs_chunk user_chunk;
		uint32_t __user *cdata;

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		chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
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		if (copy_from_user(&user_chunk, chunk_ptr,
				       sizeof(struct drm_amdgpu_cs_chunk))) {
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			ret = -EFAULT;
			i--;
			goto free_partial_kdata;
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		}
		p->chunks[i].chunk_id = user_chunk.chunk_id;
		p->chunks[i].length_dw = user_chunk.length_dw;

		size = p->chunks[i].length_dw;
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		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
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		p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
		if (p->chunks[i].kdata == NULL) {
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			ret = -ENOMEM;
			i--;
			goto free_partial_kdata;
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		}
		size *= sizeof(uint32_t);
		if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
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			ret = -EFAULT;
			goto free_partial_kdata;
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		}

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		switch (p->chunks[i].chunk_id) {
		case AMDGPU_CHUNK_ID_IB:
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			++num_ibs;
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			break;

		case AMDGPU_CHUNK_ID_FENCE:
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			size = sizeof(struct drm_amdgpu_cs_chunk_fence);
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			if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
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				ret = -EINVAL;
				goto free_partial_kdata;
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			}
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			ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
							 &uf_offset);
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			if (ret)
				goto free_partial_kdata;

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			break;

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		case AMDGPU_CHUNK_ID_DEPENDENCIES:
			break;

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		default:
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			ret = -EINVAL;
			goto free_partial_kdata;
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		}
	}

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	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
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	if (ret)
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		goto free_all_kdata;
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	if (p->uf_entry.robj)
		p->job->uf_addr = uf_offset;
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	kfree(chunk_array);
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	return 0;

free_all_kdata:
	i = p->nchunks - 1;
free_partial_kdata:
	for (; i >= 0; i--)
		drm_free_large(p->chunks[i].kdata);
	kfree(p->chunks);
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put_ctx:
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	amdgpu_ctx_put(p->ctx);
free_chunk:
	kfree(chunk_array);

	return ret;
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}

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/* Convert microseconds to bytes. */
static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
{
	if (us <= 0 || !adev->mm_stats.log2_max_MBps)
		return 0;

	/* Since accum_us is incremented by a million per second, just
	 * multiply it by the number of MB/s to get the number of bytes.
	 */
	return us << adev->mm_stats.log2_max_MBps;
}

static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
{
	if (!adev->mm_stats.log2_max_MBps)
		return 0;

	return bytes >> adev->mm_stats.log2_max_MBps;
}

/* Returns how many bytes TTM can move right now. If no bytes can be moved,
 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 * which means it can go over the threshold once. If that happens, the driver
 * will be in debt and no other buffer migrations can be done until that debt
 * is repaid.
 *
 * This approach allows moving a buffer of any size (it's important to allow
 * that).
 *
 * The currency is simply time in microseconds and it increases as the clock
 * ticks. The accumulated microseconds (us) are converted to bytes and
 * returned.
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 */
static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
{
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	s64 time_us, increment_us;
	u64 max_bytes;
	u64 free_vram, total_vram, used_vram;
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	/* Allow a maximum of 200 accumulated ms. This is basically per-IB
	 * throttling.
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	 *
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	 * It means that in order to get full max MBps, at least 5 IBs per
	 * second must be submitted and not more than 200ms apart from each
	 * other.
	 */
	const s64 us_upper_bound = 200000;
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	if (!adev->mm_stats.log2_max_MBps)
		return 0;

	total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
	used_vram = atomic64_read(&adev->vram_usage);
	free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;

	spin_lock(&adev->mm_stats.lock);

	/* Increase the amount of accumulated us. */
	time_us = ktime_to_us(ktime_get());
	increment_us = time_us - adev->mm_stats.last_update_us;
	adev->mm_stats.last_update_us = time_us;
	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
                                      us_upper_bound);

	/* This prevents the short period of low performance when the VRAM
	 * usage is low and the driver is in debt or doesn't have enough
	 * accumulated us to fill VRAM quickly.
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	 *
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	 * The situation can occur in these cases:
	 * - a lot of VRAM is freed by userspace
	 * - the presence of a big buffer causes a lot of evictions
	 *   (solution: split buffers into smaller ones)
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	 *
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	 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
	 * accum_us to a positive number.
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	 */
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	if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
		s64 min_us;

		/* Be more aggresive on dGPUs. Try to fill a portion of free
		 * VRAM now.
		 */
		if (!(adev->flags & AMD_IS_APU))
			min_us = bytes_to_us(adev, free_vram / 4);
		else
			min_us = 0; /* Reset accum_us on APUs. */

		adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
	}
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	/* This returns 0 if the driver is in debt to disallow (optional)
	 * buffer moves.
	 */
	max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);

	spin_unlock(&adev->mm_stats.lock);
	return max_bytes;
}

/* Report how many bytes have really been moved for the last command
 * submission. This can result in a debt that can stop buffer migrations
 * temporarily.
 */
static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev,
					 u64 num_bytes)
{
	spin_lock(&adev->mm_stats.lock);
	adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
	spin_unlock(&adev->mm_stats.lock);
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}

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static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
				 struct amdgpu_bo *bo)
{
	u64 initial_bytes_moved;
	uint32_t domain;
	int r;

	if (bo->pin_count)
		return 0;

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	/* Don't move this buffer if we have depleted our allowance
	 * to move it. Don't move anything if the threshold is zero.
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	 */
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	if (p->bytes_moved < p->bytes_moved_threshold)
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		domain = bo->prefered_domains;
	else
		domain = bo->allowed_domains;

retry:
	amdgpu_ttm_placement_from_domain(bo, domain);
	initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
	p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
		initial_bytes_moved;

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	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
		domain = bo->allowed_domains;
		goto retry;
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	}

	return r;
}

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/* Last resort, try to evict something from the current working set */
static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
				struct amdgpu_bo_list_entry *lobj)
{
	uint32_t domain = lobj->robj->allowed_domains;
	int r;

	if (!p->evictable)
		return false;

	for (;&p->evictable->tv.head != &p->validated;
	     p->evictable = list_prev_entry(p->evictable, tv.head)) {

		struct amdgpu_bo_list_entry *candidate = p->evictable;
		struct amdgpu_bo *bo = candidate->robj;
		u64 initial_bytes_moved;
		uint32_t other;

		/* If we reached our current BO we can forget it */
		if (candidate == lobj)
			break;

		other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);

		/* Check if this BO is in one of the domains we need space for */
		if (!(other & domain))
			continue;

		/* Check if we can move this BO somewhere else */
		other = bo->allowed_domains & ~domain;
		if (!other)
			continue;

		/* Good we can try to move this BO somewhere else */
		amdgpu_ttm_placement_from_domain(bo, other);
		initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
		p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
			initial_bytes_moved;

		if (unlikely(r))
			break;

		p->evictable = list_prev_entry(p->evictable, tv.head);
		list_move(&candidate->tv.head, &p->validated);

		return true;
	}

	return false;
}

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static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
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			    struct list_head *validated)
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{
	struct amdgpu_bo_list_entry *lobj;
	int r;

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	list_for_each_entry(lobj, validated, tv.head) {
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		struct amdgpu_bo *bo = lobj->robj;
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		bool binding_userptr = false;
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		struct mm_struct *usermm;
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		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
		if (usermm && usermm != current->mm)
			return -EPERM;

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		/* Check if we have user pages and nobody bound the BO already */
		if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
			size_t size = sizeof(struct page *);

			size *= bo->tbo.ttm->num_pages;
			memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
			binding_userptr = true;
		}

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		if (p->evictable == lobj)
			p->evictable = NULL;

		do {
			r = amdgpu_cs_bo_validate(p, bo);
		} while (r == -ENOMEM && amdgpu_cs_try_evict(p, lobj));
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		if (r)
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			return r;
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		if (bo->shadow) {
			r = amdgpu_cs_bo_validate(p, bo);
			if (r)
				return r;
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		}
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		if (binding_userptr) {
			drm_free_large(lobj->user_pages);
			lobj->user_pages = NULL;
		}
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	}
	return 0;
}

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static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
				union drm_amdgpu_cs *cs)
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{
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_bo_list_entry *e;
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	struct list_head duplicates;
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	bool need_mmap_lock = false;
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	unsigned i, tries = 10;
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	int r;
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	INIT_LIST_HEAD(&p->validated);

	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
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	if (p->bo_list) {
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		need_mmap_lock = p->bo_list->first_userptr !=
			p->bo_list->num_entries;
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		amdgpu_bo_list_get_list(p->bo_list, &p->validated);
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	}
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	INIT_LIST_HEAD(&duplicates);
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	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
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	if (p->uf_entry.robj)
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		list_add(&p->uf_entry.tv.head, &p->validated);

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	if (need_mmap_lock)
		down_read(&current->mm->mmap_sem);

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	while (1) {
		struct list_head need_pages;
		unsigned i;

		r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
					   &duplicates);
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		if (unlikely(r != 0)) {
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			if (r != -ERESTARTSYS)
				DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
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			goto error_free_pages;
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		}
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		/* Without a BO list we don't have userptr BOs */
		if (!p->bo_list)
			break;

		INIT_LIST_HEAD(&need_pages);
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {

			e = &p->bo_list->array[i];

			if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
				 &e->user_invalidated) && e->user_pages) {

				/* We acquired a page array, but somebody
				 * invalidated it. Free it an try again
				 */
				release_pages(e->user_pages,
					      e->robj->tbo.ttm->num_pages,
					      false);
				drm_free_large(e->user_pages);
				e->user_pages = NULL;
			}

			if (e->robj->tbo.ttm->state != tt_bound &&
			    !e->user_pages) {
				list_del(&e->tv.head);
				list_add(&e->tv.head, &need_pages);

				amdgpu_bo_unreserve(e->robj);
			}
		}

		if (list_empty(&need_pages))
			break;

		/* Unreserve everything again. */
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);

572
		/* We tried too many times, just abort */
573
574
		if (!--tries) {
			r = -EDEADLK;
575
			DRM_ERROR("deadlock in %s\n", __func__);
576
577
578
579
580
581
582
583
584
585
586
			goto error_free_pages;
		}

		/* Fill the page arrays for all useptrs. */
		list_for_each_entry(e, &need_pages, tv.head) {
			struct ttm_tt *ttm = e->robj->tbo.ttm;

			e->user_pages = drm_calloc_large(ttm->num_pages,
							 sizeof(struct page*));
			if (!e->user_pages) {
				r = -ENOMEM;
587
				DRM_ERROR("calloc failure in %s\n", __func__);
588
589
590
591
592
				goto error_free_pages;
			}

			r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
			if (r) {
593
				DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
594
595
596
597
598
599
600
601
602
				drm_free_large(e->user_pages);
				e->user_pages = NULL;
				goto error_free_pages;
			}
		}

		/* And try again. */
		list_splice(&need_pages, &p->validated);
	}
603

604
	amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates);
605

606
607
	p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
	p->bytes_moved = 0;
608
609
610
	p->evictable = list_last_entry(&p->validated,
				       struct amdgpu_bo_list_entry,
				       tv.head);
611
612

	r = amdgpu_cs_list_validate(p, &duplicates);
613
614
	if (r) {
		DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
615
		goto error_validate;
616
	}
617

618
	r = amdgpu_cs_list_validate(p, &p->validated);
619
620
	if (r) {
		DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
621
		goto error_validate;
622
	}
623

624
625
	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved);

626
627
628
	fpriv->vm.last_eviction_counter =
		atomic64_read(&p->adev->num_evictions);

629
	if (p->bo_list) {
630
631
632
		struct amdgpu_bo *gds = p->bo_list->gds_obj;
		struct amdgpu_bo *gws = p->bo_list->gws_obj;
		struct amdgpu_bo *oa = p->bo_list->oa_obj;
633
634
635
636
637
638
639
640
		struct amdgpu_vm *vm = &fpriv->vm;
		unsigned i;

		for (i = 0; i < p->bo_list->num_entries; i++) {
			struct amdgpu_bo *bo = p->bo_list->array[i].robj;

			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
		}
641
642
643
644
645
646
647
648
649
650
651
652
653

		if (gds) {
			p->job->gds_base = amdgpu_bo_gpu_offset(gds);
			p->job->gds_size = amdgpu_bo_size(gds);
		}
		if (gws) {
			p->job->gws_base = amdgpu_bo_gpu_offset(gws);
			p->job->gws_size = amdgpu_bo_size(gws);
		}
		if (oa) {
			p->job->oa_base = amdgpu_bo_gpu_offset(oa);
			p->job->oa_size = amdgpu_bo_size(oa);
		}
654
	}
655

656
657
658
	if (!r && p->uf_entry.robj) {
		struct amdgpu_bo *uf = p->uf_entry.robj;

659
		r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
660
661
		p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
	}
662

663
error_validate:
664
665
	if (r) {
		amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
666
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
667
	}
668

669
670
error_free_pages:

671
672
673
	if (need_mmap_lock)
		up_read(&current->mm->mmap_sem);

674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
	if (p->bo_list) {
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {
			e = &p->bo_list->array[i];

			if (!e->user_pages)
				continue;

			release_pages(e->user_pages,
				      e->robj->tbo.ttm->num_pages,
				      false);
			drm_free_large(e->user_pages);
		}
	}

689
690
691
692
693
694
695
696
697
698
	return r;
}

static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
{
	struct amdgpu_bo_list_entry *e;
	int r;

	list_for_each_entry(e, &p->validated, tv.head) {
		struct reservation_object *resv = e->robj->tbo.resv;
699
		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
700
701
702
703
704
705
706

		if (r)
			return r;
	}
	return 0;
}

707
708
709
710
711
712
713
714
715
/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
716
{
717
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
718
719
	unsigned i;

720
	if (!error) {
721
722
		amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);

723
		ttm_eu_fence_buffer_objects(&parser->ticket,
724
725
					    &parser->validated,
					    parser->fence);
726
727
728
729
	} else if (backoff) {
		ttm_eu_backoff_reservation(&parser->ticket,
					   &parser->validated);
	}
730
	fence_put(parser->fence);
731

732
733
	if (parser->ctx)
		amdgpu_ctx_put(parser->ctx);
734
735
736
	if (parser->bo_list)
		amdgpu_bo_list_put(parser->bo_list);

737
738
739
	for (i = 0; i < parser->nchunks; i++)
		drm_free_large(parser->chunks[i].kdata);
	kfree(parser->chunks);
740
741
	if (parser->job)
		amdgpu_job_free(parser->job);
742
	amdgpu_bo_unref(&parser->uf_entry.robj);
743
744
745
746
747
748
749
750
751
752
753
754
755
756
}

static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
				   struct amdgpu_vm *vm)
{
	struct amdgpu_device *adev = p->adev;
	struct amdgpu_bo_va *bo_va;
	struct amdgpu_bo *bo;
	int i, r;

	r = amdgpu_vm_update_page_directory(adev, vm);
	if (r)
		return r;

757
	r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
758
759
760
	if (r)
		return r;

761
762
763
764
765
766
	r = amdgpu_vm_clear_freed(adev, vm);
	if (r)
		return r;

	if (p->bo_list) {
		for (i = 0; i < p->bo_list->num_entries; i++) {
767
768
			struct fence *f;

769
770
771
772
773
774
775
776
777
			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

			bo_va = p->bo_list->array[i].bo_va;
			if (bo_va == NULL)
				continue;

778
			r = amdgpu_vm_bo_update(adev, bo_va, false);
779
780
781
			if (r)
				return r;

782
			f = bo_va->last_pt_update;
783
			r = amdgpu_sync_fence(adev, &p->job->sync, f);
784
785
			if (r)
				return r;
786
		}
787
788
789

	}

790
	r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
791
792
793
794
795
796
797
798
799
800
801

	if (amdgpu_vm_debug && p->bo_list) {
		/* Invalidate all BOs to test for userspace bugs */
		for (i = 0; i < p->bo_list->num_entries; i++) {
			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

			amdgpu_vm_bo_invalidate(adev, bo);
		}
802
803
	}

804
	return r;
805
806
807
}

static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
808
				 struct amdgpu_cs_parser *p)
809
{
810
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
811
	struct amdgpu_vm *vm = &fpriv->vm;
812
	struct amdgpu_ring *ring = p->job->ring;
813
814
815
	int i, r;

	/* Only for UVD/VCE VM emulation */
816
	if (ring->funcs->parse_cs) {
817
		p->job->vm = NULL;
818
819
		for (i = 0; i < p->job->num_ibs; i++) {
			r = amdgpu_ring_parse_cs(ring, p, i);
820
821
822
			if (r)
				return r;
		}
823
824
	} else {
		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
825

826
827
828
829
		r = amdgpu_bo_vm_update_pte(p, vm);
		if (r)
			return r;
	}
830

831
	return amdgpu_cs_sync_rings(p);
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
}

static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
{
	if (r == -EDEADLK) {
		r = amdgpu_gpu_reset(adev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
			     struct amdgpu_cs_parser *parser)
{
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	int i, j;
	int r;

852
	for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
853
854
855
856
857
858
		struct amdgpu_cs_chunk *chunk;
		struct amdgpu_ib *ib;
		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
		struct amdgpu_ring *ring;

		chunk = &parser->chunks[i];
859
		ib = &parser->job->ibs[j];
860
861
862
863
864
865
866
867
		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;

		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
			continue;

		r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
				       chunk_ib->ip_instance, chunk_ib->ring,
				       &ring);
868
		if (r)
869
870
			return r;

871
872
873
874
875
876
877
878
		if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
			parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
			if (!parser->ctx->preamble_presented) {
				parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
				parser->ctx->preamble_presented = true;
			}
		}

879
880
881
882
883
		if (parser->job->ring && parser->job->ring != ring)
			return -EINVAL;

		parser->job->ring = ring;

884
		if (ring->funcs->parse_cs) {
885
			struct amdgpu_bo_va_mapping *m;
886
			struct amdgpu_bo *aobj = NULL;
887
888
			uint64_t offset;
			uint8_t *kptr;
889

890
891
			m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
						   &aobj);
892
893
894
			if (!aobj) {
				DRM_ERROR("IB va_start is invalid\n");
				return -EINVAL;
895
896
			}

897
898
899
900
901
902
			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
			    (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
				return -EINVAL;
			}

903
			/* the IB should be reserved at this point */
904
			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
905
906
907
908
			if (r) {
				return r;
			}

909
910
911
			offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
			kptr += chunk_ib->va_start - offset;

912
			r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
913
914
915
916
917
918
919
920
			if (r) {
				DRM_ERROR("Failed to get ib !\n");
				return r;
			}

			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
			amdgpu_bo_kunmap(aobj);
		} else {
921
			r =  amdgpu_ib_get(adev, vm, 0, ib);
922
923
924
925
926
927
928
929
			if (r) {
				DRM_ERROR("Failed to get ib !\n");
				return r;
			}

			ib->gpu_addr = chunk_ib->va_start;
		}

930
		ib->length_dw = chunk_ib->ib_bytes / 4;
931
		ib->flags = chunk_ib->flags;
932
933
934
		j++;
	}

935
	/* UVD & VCE fw doesn't support user fences */
936
	if (parser->job->uf_addr && (
937
938
939
	    parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
	    parser->job->ring->type == AMDGPU_RING_TYPE_VCE))
		return -EINVAL;
940
941
942
943

	return 0;
}

944
945
946
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
				  struct amdgpu_cs_parser *p)
{
947
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
	int i, j, r;

	for (i = 0; i < p->nchunks; ++i) {
		struct drm_amdgpu_cs_chunk_dep *deps;
		struct amdgpu_cs_chunk *chunk;
		unsigned num_deps;

		chunk = &p->chunks[i];

		if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
			continue;

		deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
		num_deps = chunk->length_dw * 4 /
			sizeof(struct drm_amdgpu_cs_chunk_dep);

		for (j = 0; j < num_deps; ++j) {
			struct amdgpu_ring *ring;
966
			struct amdgpu_ctx *ctx;
967
			struct fence *fence;
968
969
970
971
972
973
974

			r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
					       deps[j].ip_instance,
					       deps[j].ring, &ring);
			if (r)
				return r;

975
976
977
978
			ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
			if (ctx == NULL)
				return -EINVAL;

979
980
981
982
			fence = amdgpu_ctx_get_fence(ctx, ring,
						     deps[j].handle);
			if (IS_ERR(fence)) {
				r = PTR_ERR(fence);
983
				amdgpu_ctx_put(ctx);
984
				return r;
985

986
			} else if (fence) {
987
988
				r = amdgpu_sync_fence(adev, &p->job->sync,
						      fence);
989
990
991
992
993
				fence_put(fence);
				amdgpu_ctx_put(ctx);
				if (r)
					return r;
			}
994
995
996
997
998
999
		}
	}

	return 0;
}

1000
1001
1002
static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
			    union drm_amdgpu_cs *cs)
{
1003
	struct amdgpu_ring *ring = p->job->ring;
1004
	struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1005
	struct amdgpu_job *job;
1006
	int r;
1007

1008
1009
	job = p->job;
	p->job = NULL;
1010

1011
	r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1012
	if (r) {
1013
		amdgpu_job_free(job);
1014
		return r;
1015
1016
	}

1017
	job->owner = p->filp;
1018
	job->fence_ctx = entity->fence_context;
1019
1020
	p->fence = fence_get(&job->base.s_fence->finished);
	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1021
	job->uf_sequence = cs->out.handle;
1022
	amdgpu_job_free_resources(job);
1023
1024
1025
1026
1027
1028
1029

	trace_amdgpu_cs_ioctl(job);
	amd_sched_entity_push_job(&job->base);

	return 0;
}

1030
1031
1032
1033
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_cs *cs = data;
1034
	struct amdgpu_cs_parser parser = {};
1035
1036
	bool reserved_buffers = false;
	int i, r;
1037

1038
	if (!adev->accel_working)
1039
		return -EBUSY;
1040

1041
1042
1043
1044
	parser.adev = adev;
	parser.filp = filp;

	r = amdgpu_cs_parser_init(&parser, data);
1045
	if (r) {
1046
		DRM_ERROR("Failed to initialize parser !\n");
1047
		amdgpu_cs_parser_fini(&parser, r, false);
1048
1049
1050
		r = amdgpu_cs_handle_lockup(adev, r);
		return r;
	}
1051
	r = amdgpu_cs_parser_bos(&parser, data);
1052
1053
1054
1055
1056
1057
	if (r == -ENOMEM)
		DRM_ERROR("Not enough memory for command submission!\n");
	else if (r && r != -ERESTARTSYS)
		DRM_ERROR("Failed to process the buffer list %d!\n", r);
	else if (!r) {
		reserved_buffers = true;
1058
		r = amdgpu_cs_ib_fill(adev, &parser);
1059
1060
1061
	}

	if (!r) {
1062
		r = amdgpu_cs_dependencies(adev, &parser);
1063
1064
1065
1066
1067
1068
1069
		if (r)
			DRM_ERROR("Failed in the dependencies handling %d!\n", r);
	}

	if (r)
		goto out;

1070
	for (i = 0; i < parser.job->num_ibs; i++)
1071
		trace_amdgpu_cs(&parser, i);
1072

1073
	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1074
1075
1076
	if (r)
		goto out;

1077
	r = amdgpu_cs_submit(&parser, cs);
1078
1079

out:
1080
	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
	r = amdgpu_cs_handle_lockup(adev, r);
	return r;
}

/**
 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 *
 * @dev: drm device
 * @data: data from userspace
 * @filp: file private
 *
 * Wait for the command submission identified by handle to finish.
 */
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *filp)
{
	union drm_amdgpu_wait_cs *wait = data;
	struct amdgpu_device *adev = dev->dev_private;
	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1100
	struct amdgpu_ring *ring = NULL;
1101
	struct amdgpu_ctx *ctx;
1102
	struct fence *fence;
1103
1104
	long r;

1105
1106
1107
1108
1109
	r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
			       wait->in.ring, &ring);
	if (r)
		return r;

1110
1111
1112
	ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
	if (ctx == NULL)
		return -EINVAL;
1113

1114
1115
1116
1117
1118
1119
1120
1121
	fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
	if (IS_ERR(fence))
		r = PTR_ERR(fence);
	else if (fence) {
		r = fence_wait_timeout(fence, true, timeout);
		fence_put(fence);
	} else
		r = 1;
1122

1123
	amdgpu_ctx_put(ctx);
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
	if (r < 0)
		return r;

	memset(wait, 0, sizeof(*wait));
	wait->out.status = (r == 0);

	return 0;
}

/**
 * amdgpu_cs_find_bo_va - find bo_va for VM address
 *
 * @parser: command submission parser context
 * @addr: VM address
 * @bo: resulting BO of the mapping found
 *
 * Search the buffer objects in the command submission context for a certain
 * virtual memory address. Returns allocation structure when found, NULL
 * otherwise.
 */
struct amdgpu_bo_va_mapping *
amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
		       uint64_t addr, struct amdgpu_bo **bo)
{
	struct amdgpu_bo_va_mapping *mapping;
1149
1150
1151
1152
	unsigned i;

	if (!parser->bo_list)
		return NULL;
1153
1154
1155

	addr /= AMDGPU_GPU_PAGE_SIZE;

1156
1157
1158
1159
1160
	for (i = 0; i < parser->bo_list->num_entries; i++) {
		struct amdgpu_bo_list_entry *lobj;

		lobj = &parser->bo_list->array[i];
		if (!lobj->bo_va)
1161
1162
			continue;

1163
		list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1164
1165
1166
1167
			if (mapping->it.start > addr ||
			    addr > mapping->it.last)
				continue;

1168
			*bo = lobj->bo_va->bo;
1169
1170
1171
			return mapping;
		}

1172
		list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1173
1174
1175
1176
			if (mapping->it.start > addr ||
			    addr > mapping->it.last)
				continue;

1177
			*bo = lobj->bo_va->bo;
1178
1179
1180
1181
1182
1183
			return mapping;
		}
	}

	return NULL;
}
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202

/**
 * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
 *
 * @parser: command submission parser context
 *
 * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
 */
int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
{
	unsigned i;
	int r;

	if (!parser->bo_list)
		return 0;

	for (i = 0; i < parser->bo_list->num_entries; i++) {
		struct amdgpu_bo *bo = parser->bo_list->array[i].robj;

1203
		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1204
1205
1206
1207
1208
1209
		if (unlikely(r))
			return r;
	}

	return 0;
}