• Benoit Cousson's avatar
    ARM: shmobile: r8a7790/lager dts: Add DVFS parameters into cpu0 node for r8a7790 · b989e138
    Benoit Cousson authored
    
    
    Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
    
    - voltage-tolerance = 1%
      It reflects the tolerance for the CPU voltage defined inside the OPP
      table. Due to the lack of proper OPP definition, use an arbitrary safe
      value.
    - clock-latency = 300 us
      Approximate worst-case latency to do a full DVFS transition for every
      OPPs. Due to the lack of HW information, use an arbitrary safe value.
      Note: The term transition-latency will be more accurate to define this
      value since the clock transition latency is not the only parameter that
      will define the overall DVFS transition.
    - operating-points = < kHz - uV >
      List of 6 operating points. All of them are using the same voltage
      since the valid Vmin voltage is not documented in the HW spec.
    - clocks
      phandle to the CPU clock source. This clock source is used for all the
      4 CortexA15 located inside the same cluster.
    Signed-off-by: default avatarBenoit Cousson <bcousson+renesas@baylibre.com>
    [gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0]
    Signed-off-by: default avatarGaku Inami <gaku.inami.xw@bp.renesas.com>
    Acked-by: default avatarMagnus Damm <damm@opensource.se>
    Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
    b989e138
r8a7790-lager.dts 6.25 KB