Commit 11a8e778 authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds
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[PATCH] x86_64: Some housekeeping in local APIC code



Remove support for obsolete hardware and cleanup.

- Remove checks for non integrated APICs
- Replace apic_write_around with apic_write.
- Remove apic_read_around
- Remove APIC version reads used by old workarounds
- Remove old workaround for Simics
- Fix indentation
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 5f1d189f
...@@ -53,20 +53,17 @@ static void apic_pm_activate(void); ...@@ -53,20 +53,17 @@ static void apic_pm_activate(void);
void enable_NMI_through_LVT0 (void * dummy) void enable_NMI_through_LVT0 (void * dummy)
{ {
unsigned int v, ver; unsigned int v;
ver = apic_read(APIC_LVR);
ver = GET_APIC_VERSION(ver);
v = APIC_DM_NMI; /* unmask and set to NMI */ v = APIC_DM_NMI; /* unmask and set to NMI */
apic_write_around(APIC_LVT0, v); apic_write(APIC_LVT0, v);
} }
int get_maxlvt(void) int get_maxlvt(void)
{ {
unsigned int v, ver, maxlvt; unsigned int v, maxlvt;
v = apic_read(APIC_LVR); v = apic_read(APIC_LVR);
ver = GET_APIC_VERSION(v);
maxlvt = GET_APIC_MAXLVT(v); maxlvt = GET_APIC_MAXLVT(v);
return maxlvt; return maxlvt;
} }
...@@ -84,33 +81,33 @@ void clear_local_APIC(void) ...@@ -84,33 +81,33 @@ void clear_local_APIC(void)
*/ */
if (maxlvt >= 3) { if (maxlvt >= 3) {
v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
} }
/* /*
* Careful: we have to set masks only first to deassert * Careful: we have to set masks only first to deassert
* any level-triggered sources. * any level-triggered sources.
*/ */
v = apic_read(APIC_LVTT); v = apic_read(APIC_LVTT);
apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
v = apic_read(APIC_LVT0); v = apic_read(APIC_LVT0);
apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
v = apic_read(APIC_LVT1); v = apic_read(APIC_LVT1);
apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
if (maxlvt >= 4) { if (maxlvt >= 4) {
v = apic_read(APIC_LVTPC); v = apic_read(APIC_LVTPC);
apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
} }
/* /*
* Clean APIC state for other OSs: * Clean APIC state for other OSs:
*/ */
apic_write_around(APIC_LVTT, APIC_LVT_MASKED); apic_write(APIC_LVTT, APIC_LVT_MASKED);
apic_write_around(APIC_LVT0, APIC_LVT_MASKED); apic_write(APIC_LVT0, APIC_LVT_MASKED);
apic_write_around(APIC_LVT1, APIC_LVT_MASKED); apic_write(APIC_LVT1, APIC_LVT_MASKED);
if (maxlvt >= 3) if (maxlvt >= 3)
apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); apic_write(APIC_LVTERR, APIC_LVT_MASKED);
if (maxlvt >= 4) if (maxlvt >= 4)
apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); apic_write(APIC_LVTPC, APIC_LVT_MASKED);
v = GET_APIC_VERSION(apic_read(APIC_LVR)); v = GET_APIC_VERSION(apic_read(APIC_LVR));
apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0);
apic_read(APIC_ESR); apic_read(APIC_ESR);
...@@ -155,7 +152,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) ...@@ -155,7 +152,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
value &= ~APIC_VECTOR_MASK; value &= ~APIC_VECTOR_MASK;
value |= APIC_SPIV_APIC_ENABLED; value |= APIC_SPIV_APIC_ENABLED;
value |= 0xf; value |= 0xf;
apic_write_around(APIC_SPIV, value); apic_write(APIC_SPIV, value);
if (!virt_wire_setup) { if (!virt_wire_setup) {
/* For LVT0 make it edge triggered, active high, external and enabled */ /* For LVT0 make it edge triggered, active high, external and enabled */
...@@ -165,11 +162,11 @@ void disconnect_bsp_APIC(int virt_wire_setup) ...@@ -165,11 +162,11 @@ void disconnect_bsp_APIC(int virt_wire_setup)
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
apic_write_around(APIC_LVT0, value); apic_write(APIC_LVT0, value);
} }
else { else {
/* Disable LVT0 */ /* Disable LVT0 */
apic_write_around(APIC_LVT0, APIC_LVT_MASKED); apic_write(APIC_LVT0, APIC_LVT_MASKED);
} }
/* For LVT1 make it edge triggered, active high, nmi and enabled */ /* For LVT1 make it edge triggered, active high, nmi and enabled */
...@@ -180,7 +177,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) ...@@ -180,7 +177,7 @@ void disconnect_bsp_APIC(int virt_wire_setup)
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
apic_write_around(APIC_LVT1, value); apic_write(APIC_LVT1, value);
} }
} }
...@@ -196,7 +193,7 @@ void disable_local_APIC(void) ...@@ -196,7 +193,7 @@ void disable_local_APIC(void)
*/ */
value = apic_read(APIC_SPIV); value = apic_read(APIC_SPIV);
value &= ~APIC_SPIV_APIC_ENABLED; value &= ~APIC_SPIV_APIC_ENABLED;
apic_write_around(APIC_SPIV, value); apic_write(APIC_SPIV, value);
} }
/* /*
...@@ -273,7 +270,7 @@ void __init sync_Arb_IDs(void) ...@@ -273,7 +270,7 @@ void __init sync_Arb_IDs(void)
apic_wait_icr_idle(); apic_wait_icr_idle();
apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
| APIC_DM_INIT); | APIC_DM_INIT);
} }
...@@ -284,7 +281,7 @@ extern void __error_in_apic_c (void); ...@@ -284,7 +281,7 @@ extern void __error_in_apic_c (void);
*/ */
void __init init_bsp_APIC(void) void __init init_bsp_APIC(void)
{ {
unsigned int value, ver; unsigned int value;
/* /*
* Don't do the setup now if we have a SMP BIOS as the * Don't do the setup now if we have a SMP BIOS as the
...@@ -294,7 +291,6 @@ void __init init_bsp_APIC(void) ...@@ -294,7 +291,6 @@ void __init init_bsp_APIC(void)
return; return;
value = apic_read(APIC_LVR); value = apic_read(APIC_LVR);
ver = GET_APIC_VERSION(value);
/* /*
* Do not trust the local APIC being empty at bootup. * Do not trust the local APIC being empty at bootup.
...@@ -309,22 +305,21 @@ void __init init_bsp_APIC(void) ...@@ -309,22 +305,21 @@ void __init init_bsp_APIC(void)
value |= APIC_SPIV_APIC_ENABLED; value |= APIC_SPIV_APIC_ENABLED;
value |= APIC_SPIV_FOCUS_DISABLED; value |= APIC_SPIV_FOCUS_DISABLED;
value |= SPURIOUS_APIC_VECTOR; value |= SPURIOUS_APIC_VECTOR;
apic_write_around(APIC_SPIV, value); apic_write(APIC_SPIV, value);
/* /*
* Set up the virtual wire mode. * Set up the virtual wire mode.
*/ */
apic_write_around(APIC_LVT0, APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_DM_EXTINT);
value = APIC_DM_NMI; value = APIC_DM_NMI;
apic_write_around(APIC_LVT1, value); apic_write(APIC_LVT1, value);
} }
void __cpuinit setup_local_APIC (void) void __cpuinit setup_local_APIC (void)
{ {
unsigned int value, ver, maxlvt; unsigned int value, maxlvt;
value = apic_read(APIC_LVR); value = apic_read(APIC_LVR);
ver = GET_APIC_VERSION(value);
if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
__error_in_apic_c(); __error_in_apic_c();
...@@ -349,7 +344,7 @@ void __cpuinit setup_local_APIC (void) ...@@ -349,7 +344,7 @@ void __cpuinit setup_local_APIC (void)
*/ */
value = apic_read(APIC_TASKPRI); value = apic_read(APIC_TASKPRI);
value &= ~APIC_TPRI_MASK; value &= ~APIC_TPRI_MASK;
apic_write_around(APIC_TASKPRI, value); apic_write(APIC_TASKPRI, value);
/* /*
* Now that we are all set up, enable the APIC * Now that we are all set up, enable the APIC
...@@ -391,7 +386,7 @@ void __cpuinit setup_local_APIC (void) ...@@ -391,7 +386,7 @@ void __cpuinit setup_local_APIC (void)
* Set spurious IRQ vector * Set spurious IRQ vector
*/ */
value |= SPURIOUS_APIC_VECTOR; value |= SPURIOUS_APIC_VECTOR;
apic_write_around(APIC_SPIV, value); apic_write(APIC_SPIV, value);
/* /*
* Set up LVT0, LVT1: * Set up LVT0, LVT1:
...@@ -411,7 +406,7 @@ void __cpuinit setup_local_APIC (void) ...@@ -411,7 +406,7 @@ void __cpuinit setup_local_APIC (void)
value = APIC_DM_EXTINT | APIC_LVT_MASKED; value = APIC_DM_EXTINT | APIC_LVT_MASKED;
apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
} }
apic_write_around(APIC_LVT0, value); apic_write(APIC_LVT0, value);
/* /*
* only the BP should see the LINT1 NMI signal, obviously. * only the BP should see the LINT1 NMI signal, obviously.
...@@ -420,14 +415,14 @@ void __cpuinit setup_local_APIC (void) ...@@ -420,14 +415,14 @@ void __cpuinit setup_local_APIC (void)
value = APIC_DM_NMI; value = APIC_DM_NMI;
else else
value = APIC_DM_NMI | APIC_LVT_MASKED; value = APIC_DM_NMI | APIC_LVT_MASKED;
apic_write_around(APIC_LVT1, value); apic_write(APIC_LVT1, value);
{ {
unsigned oldvalue; unsigned oldvalue;
maxlvt = get_maxlvt(); maxlvt = get_maxlvt();
oldvalue = apic_read(APIC_ESR); oldvalue = apic_read(APIC_ESR);
value = ERROR_APIC_VECTOR; // enables sending errors value = ERROR_APIC_VECTOR; // enables sending errors
apic_write_around(APIC_LVTERR, value); apic_write(APIC_LVTERR, value);
/* /*
* spec says clear errors after enabling vector. * spec says clear errors after enabling vector.
*/ */
...@@ -672,17 +667,17 @@ static void __setup_APIC_LVTT(unsigned int clocks) ...@@ -672,17 +667,17 @@ static void __setup_APIC_LVTT(unsigned int clocks)
if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask))
lvtt_value |= APIC_LVT_MASKED; lvtt_value |= APIC_LVT_MASKED;
apic_write_around(APIC_LVTT, lvtt_value); apic_write(APIC_LVTT, lvtt_value);
/* /*
* Divide PICLK by 16 * Divide PICLK by 16
*/ */
tmp_value = apic_read(APIC_TDCR); tmp_value = apic_read(APIC_TDCR);
apic_write_around(APIC_TDCR, (tmp_value apic_write(APIC_TDCR, (tmp_value
& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
| APIC_TDR_DIV_16); | APIC_TDR_DIV_16);
apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
} }
static void setup_APIC_timer(unsigned int clocks) static void setup_APIC_timer(unsigned int clocks)
...@@ -691,12 +686,6 @@ static void setup_APIC_timer(unsigned int clocks) ...@@ -691,12 +686,6 @@ static void setup_APIC_timer(unsigned int clocks)
local_irq_save(flags); local_irq_save(flags);
/* For some reasons this doesn't work on Simics, so fake it for now */
if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
__setup_APIC_LVTT(clocks);
return;
}
/* wait for irq slice */ /* wait for irq slice */
if (vxtime.hpet_address) { if (vxtime.hpet_address) {
int trigger = hpet_readl(HPET_T0_CMP); int trigger = hpet_readl(HPET_T0_CMP);
...@@ -709,7 +698,7 @@ static void setup_APIC_timer(unsigned int clocks) ...@@ -709,7 +698,7 @@ static void setup_APIC_timer(unsigned int clocks)
outb_p(0x00, 0x43); outb_p(0x00, 0x43);
c2 = inb_p(0x40); c2 = inb_p(0x40);
c2 |= inb_p(0x40) << 8; c2 |= inb_p(0x40) << 8;
do { do {
c1 = c2; c1 = c2;
outb_p(0x00, 0x43); outb_p(0x00, 0x43);
c2 = inb_p(0x40); c2 = inb_p(0x40);
...@@ -800,7 +789,7 @@ void disable_APIC_timer(void) ...@@ -800,7 +789,7 @@ void disable_APIC_timer(void)
unsigned long v; unsigned long v;
v = apic_read(APIC_LVTT); v = apic_read(APIC_LVTT);
apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
} }
} }
...@@ -813,7 +802,7 @@ void enable_APIC_timer(void) ...@@ -813,7 +802,7 @@ void enable_APIC_timer(void)
unsigned long v; unsigned long v;
v = apic_read(APIC_LVTT); v = apic_read(APIC_LVTT);
apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
} }
} }
...@@ -1066,7 +1055,7 @@ int __init APIC_init_uniprocessor (void) ...@@ -1066,7 +1055,7 @@ int __init APIC_init_uniprocessor (void)
connect_bsp_APIC(); connect_bsp_APIC();
phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
apic_write_around(APIC_ID, SET_APIC_ID(boot_cpu_id)); apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
setup_local_APIC(); setup_local_APIC();
......
...@@ -910,7 +910,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in ...@@ -910,7 +910,7 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
disable_8259A_irq(0); disable_8259A_irq(0);
/* mask LVT0 */ /* mask LVT0 */
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
/* /*
* We use logical delivery to get the timer IRQ * We use logical delivery to get the timer IRQ
...@@ -1635,7 +1635,7 @@ static void enable_lapic_irq (unsigned int irq) ...@@ -1635,7 +1635,7 @@ static void enable_lapic_irq (unsigned int irq)
unsigned long v; unsigned long v;
v = apic_read(APIC_LVT0); v = apic_read(APIC_LVT0);
apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
} }
static void disable_lapic_irq (unsigned int irq) static void disable_lapic_irq (unsigned int irq)
...@@ -1643,7 +1643,7 @@ static void disable_lapic_irq (unsigned int irq) ...@@ -1643,7 +1643,7 @@ static void disable_lapic_irq (unsigned int irq)
unsigned long v; unsigned long v;
v = apic_read(APIC_LVT0); v = apic_read(APIC_LVT0);
apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
} }
static void ack_lapic_irq (unsigned int irq) static void ack_lapic_irq (unsigned int irq)
...@@ -1769,7 +1769,7 @@ static inline void check_timer(void) ...@@ -1769,7 +1769,7 @@ static inline void check_timer(void)
* the 8259A which implies the virtual wire has to be * the 8259A which implies the virtual wire has to be
* disabled in the local APIC. * disabled in the local APIC.
*/ */
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
init_8259A(1); init_8259A(1);
enable_8259A_irq(0); enable_8259A_irq(0);
...@@ -1835,21 +1835,21 @@ static inline void check_timer(void) ...@@ -1835,21 +1835,21 @@ static inline void check_timer(void)
disable_8259A_irq(0); disable_8259A_irq(0);
irq_desc[0].handler = &lapic_irq_type; irq_desc[0].handler = &lapic_irq_type;
apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
enable_8259A_irq(0); enable_8259A_irq(0);
if (timer_irq_works()) { if (timer_irq_works()) {
apic_printk(APIC_QUIET, " works.\n"); apic_printk(APIC_QUIET, " works.\n");
return; return;
} }
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
apic_printk(APIC_VERBOSE," failed.\n"); apic_printk(APIC_VERBOSE," failed.\n");
apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
init_8259A(0); init_8259A(0);
make_8259A_irq(0); make_8259A_irq(0);
apic_write_around(APIC_LVT0, APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_DM_EXTINT);
unlock_ExtINT_logic(); unlock_ExtINT_logic();
......
...@@ -80,7 +80,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c) ...@@ -80,7 +80,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
h = THERMAL_APIC_VECTOR; h = THERMAL_APIC_VECTOR;
h |= (APIC_DM_FIXED | APIC_LVT_MASKED); h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
apic_write_around(APIC_LVTTHMR, h); apic_write(APIC_LVTTHMR, h);
rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h); wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
...@@ -89,7 +89,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c) ...@@ -89,7 +89,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h); wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
l = apic_read(APIC_LVTTHMR); l = apic_read(APIC_LVTTHMR);
apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n", printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
cpu, tm2 ? "TM2" : "TM1"); cpu, tm2 ? "TM2" : "TM1");
return; return;
......
...@@ -666,7 +666,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta ...@@ -666,7 +666,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
for (j = 1; j <= num_starts; j++) { for (j = 1; j <= num_starts; j++) {
Dprintk("Sending STARTUP #%d.\n",j); Dprintk("Sending STARTUP #%d.\n",j);
apic_read_around(APIC_SPIV);
apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0);
apic_read(APIC_ESR); apic_read(APIC_ESR);
Dprintk("After apic_write.\n"); Dprintk("After apic_write.\n");
...@@ -705,7 +704,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta ...@@ -705,7 +704,6 @@ static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int sta
* Due to the Pentium erratum 3AP. * Due to the Pentium erratum 3AP.
*/ */
if (maxlvt > 3) { if (maxlvt > 3) {
apic_read_around(APIC_SPIV);
apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0);
} }
accept_status = (apic_read(APIC_ESR) & 0xEF); accept_status = (apic_read(APIC_ESR) & 0xEF);
...@@ -842,11 +840,8 @@ do_rest: ...@@ -842,11 +840,8 @@ do_rest:
/* /*
* Be paranoid about clearing APIC errors. * Be paranoid about clearing APIC errors.
*/ */
if (APIC_INTEGRATED(apic_version[apicid])) { apic_write(APIC_ESR, 0);
apic_read_around(APIC_SPIV); apic_read(APIC_ESR);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
}
/* /*
* Status is now clean * Status is now clean
...@@ -1024,7 +1019,7 @@ static int __init smp_sanity_check(unsigned max_cpus) ...@@ -1024,7 +1019,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
/* /*
* If we couldn't find a local APIC, then get out of here now! * If we couldn't find a local APIC, then get out of here now!
*/ */
if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) { if (!cpu_has_apic) {
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
boot_cpu_id); boot_cpu_id);
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
......
...@@ -52,10 +52,6 @@ static __inline__ void apic_wait_icr_idle(void) ...@@ -52,10 +52,6 @@ static __inline__ void apic_wait_icr_idle(void)
while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY ); while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
} }
#define FORCE_READ_AROUND_WRITE 0
#define apic_read_around(x)
#define apic_write_around(x,y) apic_write((x),(y))
static inline void ack_APIC_irq(void) static inline void ack_APIC_irq(void)
{ {
/* /*
...@@ -66,7 +62,7 @@ static inline void ack_APIC_irq(void) ...@@ -66,7 +62,7 @@ static inline void ack_APIC_irq(void)
*/ */
/* Docs say use 0 for future compatibility */ /* Docs say use 0 for future compatibility */
apic_write_around(APIC_EOI, 0); apic_write(APIC_EOI, 0);
} }
extern int get_maxlvt (void); extern int get_maxlvt (void);
......
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