Commit 4e5df806 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://

* 'for-linus' of git:// (21 commits)
  amd64_edac: bump driver version
  amd64_edac: fix use-uninitialised bug
  amd64_edac: correct sys address to chip select mapping
  amd64_edac: add a leaner syndrome decoding algorithm
  amd64_edac: remove early hw support check
  amd64_edac: detect DDR3 memory type
  edac: add memory types strings for debugging
  edac, mce: update AMD F10h revD check
  amd64_edac: remove unneeded extract_error_address wrapper
  amd64_edac: rename StinkyIdentifier
  amd64_edac: remove superfluous dbg printk
  amd64_edac: enhance address to DRAM bank mapping
  amd64_edac: cleanup f10_early_channel_count
  amd64_edac: dump DIMM sizes on K8 too
  amd64_edac: cleanup rest of amd64_dump_misc_regs
  amd64_edac: cleanup DRAM cfg low debug output
  amd64_edac: wrap-up pci config read error handling
  amd64_edac: unify MCGCTL ECC switching
  cpumask: use modern cpumask style in drivers/edac/amd64_edac.c
  amd64_edac: make DRAM regions output more human-readable
parents aa2cf420 df5b1606
This diff is collapsed.
......@@ -129,24 +129,22 @@
* sections 3.5.4 and 3.5.5 for more information.
#define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__
#define EDAC_AMD64_VERSION " Ver: 3.3.0 " __DATE__
#define EDAC_MOD_STR "amd64_edac"
/* Extended Model from CPUID, for CPU Revision numbers */
/* NPT processors have the following Extended Models */
#define K8_REV_D 1
#define K8_REV_E 2
#define K8_REV_F 4
/* Hardware limit on ChipSelect rows per MC and processors per system */
#define MAX_CS_COUNT 8
#define DRAM_REG_COUNT 8
#define ON true
#define OFF false
* PCI-defined configuration space registers
......@@ -241,7 +239,7 @@
#define F10_DCHR_1 0x194
#define F10_DCHR_Ddr3Mode BIT(8)
#define DDR3_MODE BIT(8)
#define F10_DCHR_MblMode BIT(6)
......@@ -382,14 +380,9 @@ enum {
#define K8_NBCAP_CORES (BIT(12)|BIT(13))
#define K8_NBCAP_SECDED BIT(3)
#define K8_NBCAP_8_NODE BIT(2)
#define K8_NBCAP_DCT_DUAL BIT(0)
* MSR Regs
#define K8_MSR_MCGCTL 0x017b
/* MSRs */
#define K8_MSR_MCGCTL_NBE BIT(4)
#define K8_MSR_MC4CTL 0x0410
......@@ -487,7 +480,6 @@ struct amd64_pvt {
/* Save old hw registers' values before we modified them */
u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
u32 old_nbctl;
unsigned long old_mcgctl; /* per core on this node */
/* MC Type Index value: socket F vs Family 10h */
u32 mc_type_index;
......@@ -495,6 +487,7 @@ struct amd64_pvt {
/* misc settings */
struct flags {
unsigned long cf8_extcfg:1;
unsigned long ecc_report:1;
} flags;
......@@ -504,7 +497,6 @@ struct scrubrate {
extern struct scrubrate scrubrates[23];
extern u32 revf_quad_ddr2_shift[16];
extern const char *tt_msgs[4];
extern const char *ll_msgs[4];
extern const char *rrrr_msgs[16];
......@@ -534,17 +526,15 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
* functions and per device encoding/decoding logic.
struct low_ops {
int (*probe_valid_hardware)(struct amd64_pvt *pvt);
int (*early_channel_count)(struct amd64_pvt *pvt);
u64 (*get_error_address)(struct mem_ctl_info *mci,
struct err_regs *info);
void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
struct err_regs *info,
u64 SystemAddr);
int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
int (*early_channel_count) (struct amd64_pvt *pvt);
u64 (*get_error_address) (struct mem_ctl_info *mci,
struct err_regs *info);
void (*read_dram_base_limit) (struct amd64_pvt *pvt, int dram);
void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
struct err_regs *info, u64 SystemAddr);
int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
struct amd64_family_type {
......@@ -566,6 +556,22 @@ static inline struct low_ops *family_ops(int index)
return &amd64_family_types[index].ops;
static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
u32 *val, const char *func)
int err = 0;
err = pci_read_config_dword(pdev, offset, val);
if (err)
amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
func, PCI_FUNC(pdev->devfn), offset);
return err;
#define amd64_read_pci_cfg(pdev, offset, val) \
amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
* For future CPU versions, verify the following as new 'slow' rates appear and
* modify the necessary skip values for the supported CPU.
......@@ -74,6 +74,7 @@
extern int edac_debug_level;
extern const char *edac_mem_types[];
#define edac_debug_printk(level, fmt, arg...) \
......@@ -76,6 +76,30 @@ static void edac_mc_dump_mci(struct mem_ctl_info *mci)
debugf3("\tpvt_info = %p\n\n", mci->pvt_info);
* keep those in sync with the enum mem_type
const char *edac_mem_types[] = {
"Empty csrow",
"Reserved csrow type",
"Unknown csrow type",
"Fast page mode RAM",
"Extended data out RAM",
"Burst Extended data out RAM",
"Single data rate SDRAM",
"Registered single data rate SDRAM",
"Double data rate SDRAM",
"Registered Double data rate SDRAM",
"Rambus DRAM",
"Unbuffered DDR2 RAM",
"Fully buffered DDR2",
"Registered DDR2 RAM",
"Rambus XDR",
"Unbuffered DDR3 RAM",
"Registered DDR3 RAM",
#endif /* CONFIG_EDAC_DEBUG */
/* 'ptr' points to a possibly unaligned item X such that sizeof(X) is 'size'.
......@@ -306,7 +306,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
* value encoding has changed so interpret those differently
if ((boot_cpu_data.x86 == 0x10) &&
(boot_cpu_data.x86_model > 8)) {
(boot_cpu_data.x86_model > 7)) {
if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
} else {
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