Commit 55faed1e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6

parents 946e91f3 0edd5b44
......@@ -2058,6 +2058,13 @@ config BNX2
To compile this driver as a module, choose M here: the module
will be called bnx2. This is recommended.
config SPIDER_NET
tristate "Spider Gigabit Ethernet driver"
depends on PCI && PPC_BPA
help
This driver supports the Gigabit Ethernet chips present on the
Cell Processor-Based Blades from IBM.
config GIANFAR
tristate "Gianfar Ethernet"
depends on 85xx || 83xx
......
......@@ -54,6 +54,8 @@ obj-$(CONFIG_STNIC) += stnic.o 8390.o
obj-$(CONFIG_FEALNX) += fealnx.o
obj-$(CONFIG_TIGON3) += tg3.o
obj-$(CONFIG_BNX2) += bnx2.o
spidernet-y += spider_net.o spider_net_ethtool.o sungem_phy.o
obj-$(CONFIG_SPIDER_NET) += spidernet.o
obj-$(CONFIG_TC35815) += tc35815.o
obj-$(CONFIG_SKGE) += skge.o
obj-$(CONFIG_SK98LIN) += sk98lin/
......
......@@ -275,7 +275,7 @@ static int __init ac_probe1(int ioaddr, struct net_device *dev)
return 0;
out2:
if (ei_status.reg0)
iounmap((void *)dev->mem_start);
iounmap(ei_status.mem);
out1:
free_irq(dev->irq, dev);
out:
......
......@@ -235,7 +235,7 @@ struct lance_private {
#define MEM lp->mem
#define DREG IO->data
#define AREG IO->addr
#define REGA(a) ( AREG = (a), DREG )
#define REGA(a) (*( AREG = (a), &DREG ))
/* Definitions for packet buffer access: */
#define PKT_BUF_SZ 1544
......
......@@ -1140,7 +1140,7 @@ dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
}
static int
dm9000_drv_suspend(struct device *dev, u32 state, u32 level)
dm9000_drv_suspend(struct device *dev, pm_message_t state, u32 level)
{
struct net_device *ndev = dev_get_drvdata(dev);
......
......@@ -1372,7 +1372,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
/* synchronized against open : rtnl_lock() held by caller */
if (netif_running(dev)) {
u8 *base = get_hwbase(dev);
u8 __iomem *base = get_hwbase(dev);
/*
* It seems that the nic preloads valid ring entries into an
* internal buffer. The procedure for flushing everything is
......@@ -1423,7 +1423,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
static void nv_copy_mac_to_hw(struct net_device *dev)
{
u8 *base = get_hwbase(dev);
u8 __iomem *base = get_hwbase(dev);
u32 mac[2];
mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
......
......@@ -4,6 +4,7 @@
* Copyright (C) 2001 Kyle A. Lucke (klucke@us.ibm.com), IBM Corp.
* Substantially cleaned up by:
* Copyright (C) 2003 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
* Copyright (C) 2004-2005 Michael Ellerman, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
......
/************************************************************************
* regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
* regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
* Copyright(c) 2002-2005 Neterion Inc.
* This software may be used and distributed according to the terms of
......@@ -713,13 +713,16 @@ typedef struct _XENA_dev_config {
u64 mc_err_reg;
#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18)
#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20)
#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
#define MC_ERR_REG_SM_ERR BIT(31)
#define MC_ERR_REG_ECC_ALL_SNG (BIT(6) | \
BIT(7) | BIT(17) | BIT(19))
#define MC_ERR_REG_ECC_ALL_DBL (BIT(14) | \
BIT(15) | BIT(18) | BIT(20))
#define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
BIT(6) | BIT(7) | BIT(17) | BIT(19))
#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\
BIT(13) | BIT(14) | BIT(15) |\
BIT(18) | BIT(20))
u64 mc_err_mask;
u64 mc_err_alarm;
......
/************************************************************************
* s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
* s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
* Copyright(c) 2002-2005 Neterion Inc.
* This software may be used and distributed according to the terms of
......@@ -28,7 +28,7 @@
* explaination of all the variables.
* rx_ring_num : This can be used to program the number of receive rings used
* in the driver.
* rx_ring_len: This defines the number of descriptors each ring can have. This
* rx_ring_sz: This defines the number of descriptors each ring can have. This
* is also an array of size 8.
* tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
* tx_fifo_len: This too is an array of 8. Each element defines the number of
......@@ -67,7 +67,7 @@
/* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion";
static char s2io_driver_version[] = "Version 2.0.3.1";
static char s2io_driver_version[] = "Version 2.0.8.1";
static inline int RXD_IS_UP2DT(RxD_t *rxdp)
{
......@@ -404,7 +404,7 @@ static int init_shared_mem(struct s2io_nic *nic)
config->tx_cfg[i].fifo_len - 1;
mac_control->fifos[i].fifo_no = i;
mac_control->fifos[i].nic = nic;
mac_control->fifos[i].max_txds = MAX_SKB_FRAGS;
mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;
for (j = 0; j < page_num; j++) {
int k = 0;
......@@ -418,6 +418,26 @@ static int init_shared_mem(struct s2io_nic *nic)
DBG_PRINT(ERR_DBG, "failed for TxDL\n");
return -ENOMEM;
}
/* If we got a zero DMA address(can happen on
* certain platforms like PPC), reallocate.
* Store virtual address of page we don't want,
* to be freed later.
*/
if (!tmp_p) {
mac_control->zerodma_virt_addr = tmp_v;
DBG_PRINT(INIT_DBG,
"%s: Zero DMA address for TxDL. ", dev->name);
DBG_PRINT(INIT_DBG,
"Virtual address %llx\n", (u64)tmp_v);
tmp_v = pci_alloc_consistent(nic->pdev,
PAGE_SIZE, &tmp_p);
if (!tmp_v) {
DBG_PRINT(ERR_DBG,
"pci_alloc_consistent ");
DBG_PRINT(ERR_DBG, "failed for TxDL\n");
return -ENOMEM;
}
}
while (k < lst_per_page) {
int l = (j * lst_per_page) + k;
if (l == config->tx_cfg[i].fifo_len)
......@@ -600,7 +620,7 @@ static void free_shared_mem(struct s2io_nic *nic)
mac_info_t *mac_control;
struct config_param *config;
int lst_size, lst_per_page;
struct net_device *dev = nic->dev;
if (!nic)
return;
......@@ -616,9 +636,10 @@ static void free_shared_mem(struct s2io_nic *nic)
lst_per_page);
for (j = 0; j < page_num; j++) {
int mem_blks = (j * lst_per_page);
if ((!mac_control->fifos[i].list_info) ||
(!mac_control->fifos[i].list_info[mem_blks].
list_virt_addr))
if (!mac_control->fifos[i].list_info)
return;
if (!mac_control->fifos[i].list_info[mem_blks].
list_virt_addr)
break;
pci_free_consistent(nic->pdev, PAGE_SIZE,
mac_control->fifos[i].
......@@ -628,6 +649,18 @@ static void free_shared_mem(struct s2io_nic *nic)
list_info[mem_blks].
list_phy_addr);
}
/* If we got a zero DMA address during allocation,
* free the page now
*/
if (mac_control->zerodma_virt_addr) {
pci_free_consistent(nic->pdev, PAGE_SIZE,
mac_control->zerodma_virt_addr,
(dma_addr_t)0);
DBG_PRINT(INIT_DBG,
"%s: Freeing TxDL with zero DMA addr. ", dev->name);
DBG_PRINT(INIT_DBG, "Virtual address %llx\n",
(u64)(mac_control->zerodma_virt_addr));
}
kfree(mac_control->fifos[i].list_info);
}
......@@ -2479,9 +2512,10 @@ static void rx_intr_handler(ring_info_t *ring_data)
#endif
spin_lock(&nic->rx_lock);
if (atomic_read(&nic->card_state) == CARD_DOWN) {
DBG_PRINT(ERR_DBG, "%s: %s going down for reset\n",
DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
__FUNCTION__, dev->name);
spin_unlock(&nic->rx_lock);
return;
}
get_info = ring_data->rx_curr_get_info;
......@@ -2596,8 +2630,14 @@ static void tx_intr_handler(fifo_info_t *fifo_data)
if (txdlp->Control_1 & TXD_T_CODE) {
unsigned long long err;
err = txdlp->Control_1 & TXD_T_CODE;
DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
err);
if ((err >> 48) == 0xA) {
DBG_PRINT(TX_DBG, "TxD returned due \
to loss of link\n");
}
else {
DBG_PRINT(ERR_DBG, "***TxD error \
%llx\n", err);
}
}
skb = (struct sk_buff *) ((unsigned long)
......@@ -2689,12 +2729,16 @@ static void alarm_intr_handler(struct s2io_nic *nic)
if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
nic->mac_control.stats_info->sw_stat.
double_ecc_errs++;
DBG_PRINT(ERR_DBG, "%s: Device indicates ",
DBG_PRINT(INIT_DBG, "%s: Device indicates ",
dev->name);
DBG_PRINT(ERR_DBG, "double ECC error!!\n");
DBG_PRINT(INIT_DBG, "double ECC error!!\n");
if (nic->device_type != XFRAME_II_DEVICE) {
netif_stop_queue(dev);
schedule_work(&nic->rst_timer_task);
/* Reset XframeI only if critical error */
if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
netif_stop_queue(dev);
schedule_work(&nic->rst_timer_task);
}
}
} else {
nic->mac_control.stats_info->sw_stat.
......@@ -2706,7 +2750,8 @@ static void alarm_intr_handler(struct s2io_nic *nic)
val64 = readq(&bar0->serr_source);
if (val64 & SERR_SOURCE_ANY) {
DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
DBG_PRINT(ERR_DBG, "serious error!!\n");
DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
(unsigned long long)val64);
netif_stop_queue(dev);
schedule_work(&nic->rst_timer_task);
}
......@@ -3130,7 +3175,7 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
/* Avoid "put" pointer going beyond "get" pointer */
if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
netif_stop_queue(dev);
dev_kfree_skb(skb);
spin_unlock_irqrestore(&sp->tx_lock, flags);
......@@ -3528,7 +3573,7 @@ static void s2io_set_multicast(struct net_device *dev)
val64 = readq(&bar0->mac_cfg);
sp->promisc_flg = 1;
DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n",
DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
dev->name);
} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
/* Remove the NIC from promiscuous mode */
......@@ -3543,7 +3588,7 @@ static void s2io_set_multicast(struct net_device *dev)
val64 = readq(&bar0->mac_cfg);
sp->promisc_flg = 0;
DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n",
DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
dev->name);
}
......@@ -5325,7 +5370,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
break;
}
}
config->max_txds = MAX_SKB_FRAGS;
config->max_txds = MAX_SKB_FRAGS + 1;
/* Rx side parameters. */
if (rx_ring_sz[0] == 0)
......@@ -5525,9 +5570,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
if (sp->device_type & XFRAME_II_DEVICE) {
DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
dev->name);
DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n",
DBG_PRINT(ERR_DBG, "(rev %d), %s",
get_xena_rev_id(sp->pdev),
s2io_driver_version);
#ifdef CONFIG_2BUFF_MODE
DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
#endif
DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
sp->def_mac_addr[0].mac_addr[0],
sp->def_mac_addr[0].mac_addr[1],
......@@ -5544,9 +5594,13 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
} else {
DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
dev->name);
DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n",
DBG_PRINT(ERR_DBG, "(rev %d), %s",
get_xena_rev_id(sp->pdev),
s2io_driver_version);
#ifdef CONFIG_2BUFF_MODE
DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
#endif
DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
sp->def_mac_addr[0].mac_addr[0],
sp->def_mac_addr[0].mac_addr[1],
......
/************************************************************************
* s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
* s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
* Copyright(c) 2002-2005 Neterion Inc.
* This software may be used and distributed according to the terms of
......@@ -622,6 +622,9 @@ typedef struct mac_info {
/* Fifo specific structure */
fifo_info_t fifos[MAX_TX_FIFOS];
/* Save virtual address of TxD page with zero DMA addr(if any) */
void *zerodma_virt_addr;
/* rx side stuff */
/* Ring specific structure */
ring_info_t rings[MAX_RX_RINGS];
......
This diff is collapsed.
/*
* Network device driver for Cell Processor-Based Blade
*
* (C) Copyright IBM Corp. 2005
*
* Authors : Utz Bacher <utz.bacher@de.ibm.com>
* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SPIDER_NET_H
#define _SPIDER_NET_H
#include "sungem_phy.h"
extern int spider_net_stop(struct net_device *netdev);
extern int spider_net_open(struct net_device *netdev);
extern struct ethtool_ops spider_net_ethtool_ops;
extern char spider_net_driver_name[];
#define SPIDER_NET_MAX_MTU 2308
#define SPIDER_NET_MIN_MTU 64
#define SPIDER_NET_RXBUF_ALIGN 128
#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 64
#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
#define SPIDER_NET_RX_DESCRIPTORS_MAX 256
#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 64
#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
#define SPIDER_NET_TX_DESCRIPTORS_MAX 256
#define SPIDER_NET_RX_CSUM_DEFAULT 1
#define SPIDER_NET_WATCHDOG_TIMEOUT 5*HZ
#define SPIDER_NET_NAPI_WEIGHT 64
#define SPIDER_NET_FIRMWARE_LEN 1024
#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
/** spider_net SMMIO registers */
#define SPIDER_NET_GHIINT0STS 0x00000000
#define SPIDER_NET_GHIINT1STS 0x00000004
#define SPIDER_NET_GHIINT2STS 0x00000008
#define SPIDER_NET_GHIINT0MSK 0x00000010
#define SPIDER_NET_GHIINT1MSK 0x00000014
#define SPIDER_NET_GHIINT2MSK 0x00000018
#define SPIDER_NET_GRESUMINTNUM 0x00000020
#define SPIDER_NET_GREINTNUM 0x00000024
#define SPIDER_NET_GFFRMNUM 0x00000028
#define SPIDER_NET_GFAFRMNUM 0x0000002c
#define SPIDER_NET_GFBFRMNUM 0x00000030
#define SPIDER_NET_GFCFRMNUM 0x00000034
#define SPIDER_NET_GFDFRMNUM 0x00000038
/* clear them (don't use it) */
#define SPIDER_NET_GFREECNNUM 0x0000003c
#define SPIDER_NET_GONETIMENUM 0x00000040
#define SPIDER_NET_GTOUTFRMNUM 0x00000044
#define SPIDER_NET_GTXMDSET 0x00000050
#define SPIDER_NET_GPCCTRL 0x00000054
#define SPIDER_NET_GRXMDSET 0x00000058
#define SPIDER_NET_GIPSECINIT 0x0000005c
#define SPIDER_NET_GFTRESTRT 0x00000060
#define SPIDER_NET_GRXDMAEN 0x00000064
#define SPIDER_NET_GMRWOLCTRL 0x00000068
#define SPIDER_NET_GPCWOPCMD 0x0000006c
#define SPIDER_NET_GPCROPCMD 0x00000070
#define SPIDER_NET_GTTFRMCNT 0x00000078
#define SPIDER_NET_GTESTMD 0x0000007c
#define SPIDER_NET_GSINIT 0x00000080
#define SPIDER_NET_GSnPRGADR 0x00000084
#define SPIDER_NET_GSnPRGDAT 0x00000088
#define SPIDER_NET_GMACOPEMD 0x00000100
#define SPIDER_NET_GMACLENLMT 0x00000108
#define SPIDER_NET_GMACINTEN 0x00000118
#define SPIDER_NET_GMACPHYCTRL 0x00000120
#define SPIDER_NET_GMACAPAUSE 0x00000154
#define SPIDER_NET_GMACTXPAUSE 0x00000164
#define SPIDER_NET_GMACMODE 0x000001b0
#define SPIDER_NET_GMACBSTLMT 0x000001b4
#define SPIDER_NET_GMACUNIMACU 0x000001c0
#define SPIDER_NET_GMACUNIMACL 0x000001c8
#define SPIDER_NET_GMRMHFILnR 0x00000400
#define SPIDER_NET_MULTICAST_HASHES 256
#define SPIDER_NET_GMRUAFILnR 0x00000500
#define SPIDER_NET_GMRUA0FIL15R 0x00000578
/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
* 0x00000b.. for DMA controller B, etc. */
#define SPIDER_NET_GDADCHA 0x00000a00
#define SPIDER_NET_GDADMACCNTR 0x00000a04
#define SPIDER_NET_GDACTDPA 0x00000a08
#define SPIDER_NET_GDACTDCNT 0x00000a0c
#define SPIDER_NET_GDACDBADDR 0x00000a20
#define SPIDER_NET_GDACDBSIZE 0x00000a24
#define SPIDER_NET_GDACNEXTDA 0x00000a28
#define SPIDER_NET_GDACCOMST 0x00000a2c
#define SPIDER_NET_GDAWBCOMST 0x00000a30
#define SPIDER_NET_GDAWBRSIZE 0x00000a34
#define SPIDER_NET_GDAWBVSIZE 0x00000a38
#define SPIDER_NET_GDAWBTRST 0x00000a3c
#define SPIDER_NET_GDAWBTRERR 0x00000a40
/* TX DMA controller registers */
#define SPIDER_NET_GDTDCHA 0x00000e00
#define SPIDER_NET_GDTDMACCNTR 0x00000e04
#define SPIDER_NET_GDTCDPA 0x00000e08
#define SPIDER_NET_GDTDMASEL 0x00000e14
#define SPIDER_NET_ECMODE 0x00000f00
/* clock and reset control register */
#define SPIDER_NET_CKRCTRL 0x00000ff0
/** SCONFIG registers */
#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
/** hardcoded register values */
#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe3ff
#define SPIDER_NET_INT1_MASK_VALUE 0xffffffff
/* no MAC aborts -> auto retransmission */
#define SPIDER_NET_INT2_MASK_VALUE 0xfffffff1
/* clear counter when interrupt sources are cleared
#define SPIDER_NET_FRAMENUM_VALUE 0x0001f001 */
/* we rely on flagged descriptor interrupts */
#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
/* set this first, then the FRAMENUM_VALUE */
#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
#define SPIDER_NET_RXMODE_VALUE 0x00000011
/* auto retransmission in case of MAC aborts */
#define SPIDER_NET_TXMODE_VALUE 0x00010000
#define SPIDER_NET_RESTART_VALUE 0x00000000
#define SPIDER_NET_WOL_VALUE 0x00001111
#if 0
#define SPIDER_NET_WOL_VALUE 0x00000000
#endif
#define SPIDER_NET_IPSECINIT_VALUE 0x00f000f8
/* pause frames: automatic, no upper retransmission count */
/* outside loopback mode: ETOMOD signal dont matter, not connected */
#define SPIDER_NET_OPMODE_VALUE 0x00000063
/*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/
#define SPIDER_NET_LENLMT_VALUE 0x00000908
#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
#define SPIDER_NET_MACMODE_VALUE 0x00000001
#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
/* 1(0) enable r/tx dma
* 0000000 fixed to 0
*
* 000000 fixed to 0
* 0(1) en/disable descr writeback on force end
* 0(1) force end
*
* 000000 fixed to 0
* 00 burst alignment: 128 bytes
*
* 00000 fixed to 0
* 0 descr writeback size 32 bytes
* 0(1) descr chain end interrupt enable
* 0(1) descr status writeback enable */
/* to set RX_DMA_EN */
#define SPIDER_NET_DMA_RX_VALUE 0x80000000
#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
/* to set TX_DMA_EN */
#define SPIDER_NET_DMA_TX_VALUE 0x80000000
#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
#define SPIDER_NET_PROMISC_VALUE 0x00080000
#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
#define SPIDER_NET_DMASEL_VALUE 0x00000001
#define SPIDER_NET_ECMODE_VALUE 0x00000000
#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
* with 1 << SPIDER_NET_... */
enum spider_net_int0_status {
SPIDER_NET_GPHYINT = 0,
SPIDER_NET_GMAC2INT,
SPIDER_NET_GMAC1INT,
SPIDER_NET_GIPSINT,
SPIDER_NET_GFIFOINT,
SPIDER_NET_GDMACINT,
SPIDER_NET_GSYSINT,
SPIDER_NET_GPWOPCMPINT,
SPIDER_NET_GPROPCMPINT,
SPIDER_NET_GPWFFINT,
SPIDER_NET_GRMDADRINT,
SPIDER_NET_GRMARPINT,
SPIDER_NET_GRMMPINT,
SPIDER_NET_GDTDEN0INT,
SPIDER_NET_GDDDEN0INT,
SPIDER_NET_GDCDEN0INT,
SPIDER_NET_GDBDEN0INT,
SPIDER_NET_GDADEN0INT,
SPIDER_NET_GDTFDCINT,
SPIDER_NET_GDDFDCINT,
SPIDER_NET_GDCFDCINT,
SPIDER_NET_GDBFDCINT,
SPIDER_NET_GDAFDCINT,
SPIDER_NET_GTTEDINT,
SPIDER_NET_GDTDCEINT,
SPIDER_NET_GRFDNMINT,
SPIDER_NET_GRFCNMINT,
SPIDER_NET_GRFBNMINT,
SPIDER_NET_GRFANMINT,
SPIDER_NET_GRFNMINT,
SPIDER_NET_G1TMCNTINT,
SPIDER_NET_GFREECNTINT
};
/* GHIINT1STS bits */
enum spider_net_int1_status {
SPIDER_NET_GTMFLLINT = 0,
SPIDER_NET_GRMFLLINT,
SPIDER_NET_GTMSHTINT,
SPIDER_NET_GDTINVDINT,
SPIDER_NET_GRFDFLLINT,
SPIDER_NET_GDDDCEINT,
SPIDER_NET_GDDINVDINT,
SPIDER_NET_GRFCFLLINT,
SPIDER_NET_GDCDCEINT,
SPIDER_NET_GDCINVDINT,
SPIDER_NET_GRFBFLLINT,
SPIDER_NET_GDBDCEINT,
SPIDER_NET_GDBINVDINT,
SPIDER_NET_GRFAFLLINT,
SPIDER_NET_GDADCEINT,
SPIDER_NET_GDAINVDINT,
SPIDER_NET_GDTRSERINT,
SPIDER_NET_GDDRSERINT,
SPIDER_NET_GDCRSERINT,
SPIDER_NET_GDBRSERINT,
SPIDER_NET_GDARSERINT,
SPIDER_NET_GDSERINT,
SPIDER_NET_GDTPTERINT,
SPIDER_NET_GDDPTERINT,
SPIDER_NET_GDCPTERINT,
SPIDER_NET_GDBPTERINT,
SPIDER_NET_GDAPTERINT
};
/* GHIINT2STS bits */
enum spider_net_int2_status