Commit 7ea7b880 authored by Gilles Chanteperdrix's avatar Gilles Chanteperdrix Committed by Philippe Gerum
Browse files

arm/ipipe: fixup irq_gc_lock/unlock calls

parent 82cbe34c
......@@ -310,10 +310,11 @@ static void mvebu_gpio_irq_ack(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mvebu_gpio_chip *mvchip = gc->private;
u32 mask = ~(1 << (d->irq - gc->irq_base));
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
......@@ -322,12 +323,13 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
struct mvebu_gpio_chip *mvchip = gc->private;
struct irq_chip_type *ct = irq_data_get_chip_type(d);
u32 mask = 1 << (d->irq - gc->irq_base);
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
ct->mask_cache_priv &= ~mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
......@@ -335,13 +337,14 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mvebu_gpio_chip *mvchip = gc->private;
struct irq_chip_type *ct = irq_data_get_chip_type(d);
unsigned long flags;
u32 mask = 1 << (d->irq - gc->irq_base);
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
ct->mask_cache_priv |= mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void mvebu_gpio_level_irq_mask(struct irq_data *d)
......@@ -349,13 +352,14 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mvebu_gpio_chip *mvchip = gc->private;
struct irq_chip_type *ct = irq_data_get_chip_type(d);
unsigned long flags;
u32 mask = 1 << (d->irq - gc->irq_base);
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
ct->mask_cache_priv &= ~mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
......@@ -363,13 +367,14 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mvebu_gpio_chip *mvchip = gc->private;
struct irq_chip_type *ct = irq_data_get_chip_type(d);
unsigned long flags;
u32 mask = 1 << (d->irq - gc->irq_base);
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
ct->mask_cache_priv |= mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
/*****************************************************************************
......
......@@ -466,7 +466,7 @@ static void zynq_gpio_hold_irq(struct irq_data *irq_data)
struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
writel_relaxed(BIT(bank_pin_num),
gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
writel_relaxed(BIT(bank_pin_num),
......@@ -479,7 +479,7 @@ static void zynq_gpio_release_irq(struct irq_data *irq_data)
struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
writel_relaxed(BIT(bank_pin_num),
gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
}
......
......@@ -56,6 +56,7 @@ static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
{
struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long flags;
unsigned int idx;
chained_irq_enter(chip, desc);
......@@ -67,10 +68,10 @@ static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
unsigned long pending;
int hwirq;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
pending = irq_reg_readl(gc, b->stat_offset[idx]) &
gc->mask_cache;
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
generic_handle_irq(irq_find_mapping(b->domain,
......@@ -86,23 +87,25 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
struct bcm7120_l2_intc_data *b = gc->private;
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
if (b->can_wake)
irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
ct->regs.mask);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void bcm7120_l2_intc_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
unsigned long flags;
/* Restore the saved mask */
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static int bcm7120_l2_intc_init_one(struct device_node *dn,
......
......@@ -85,8 +85,9 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_l2_intc_data *b = gc->private;
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
/* Save the current mask */
b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS);
......@@ -95,22 +96,23 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET);
irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR);
}
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
static void brcmstb_l2_intc_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_l2_intc_data *b = gc->private;
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
/* Clear unmasked non-wakeup interrupts */
irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR);
/* Restore the saved mask */
irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET);
irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
int __init brcmstb_l2_intc_of_init(struct device_node *np,
......
......@@ -55,11 +55,12 @@ static void dw_apb_ictl_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
writel_relaxed(~0, gc->reg_base + ct->regs.enable);
writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
}
#else
#define dw_apb_ictl_resume NULL
......
......@@ -77,8 +77,9 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
u32 ctrl_off = ct->regs.type;
unsigned int src_type;
unsigned int i;
unsigned long flags;
irq_gc_lock(gc);
flags = irq_gc_lock(gc);
switch (flow_type & IRQF_TRIGGER_MASK) {
case IRQ_TYPE_EDGE_FALLING:
......@@ -95,7 +96,7 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
break;
default:
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
__func__, data->irq);
return -EBADR;
......@@ -113,7 +114,7 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
src_type_reg |= src_type;
sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags);
return IRQ_SET_MASK_OK;
}
......
......@@ -1463,7 +1463,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
u32 polarity;
u32 level;
u32 data;
unsigned long flags;
unsigned long flags, flags2;
int ret;
/* make sure the pin is configured as gpio input */
......@@ -1485,7 +1485,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
__irq_set_handler_locked(d->irq, handle_level_irq);
spin_lock_irqsave(&bank->slock, flags);
irq_gc_lock(gc);
flags2 = irq_gc_lock(gc);
level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
......@@ -1526,7 +1526,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity &= ~mask;
break;
default:
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags2);
spin_unlock_irqrestore(&bank->slock, flags);
return -EINVAL;
}
......@@ -1534,7 +1534,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags2);
spin_unlock_irqrestore(&bank->slock, flags);
return 0;
......
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