Commit 8d8706e2 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] lindent rio drivers



Run all rio files through indent -kr -i8 -bri0 -l255, as requested by Alan.

rioboot.c and rioinit.c were skipped due to worrisome lindent warnings.

Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent a9415644
......@@ -52,63 +52,57 @@ static char *_board_h_sccs_ = "@(#)board.h 1.2";
/*
** The shape of the Host Control area, at offset 0x7C00, Write Only
*/
struct s_Ctrl
{
BYTE DpCtl; /* 7C00 */
BYTE Dp_Unused2_[127];
BYTE DpIntSet; /* 7C80 */
BYTE Dp_Unused3_[127];
BYTE DpTpuReset; /* 7D00 */
BYTE Dp_Unused4_[127];
BYTE DpIntReset; /* 7D80 */
BYTE Dp_Unused5_[127];
struct s_Ctrl {
BYTE DpCtl; /* 7C00 */
BYTE Dp_Unused2_[127];
BYTE DpIntSet; /* 7C80 */
BYTE Dp_Unused3_[127];
BYTE DpTpuReset; /* 7D00 */
BYTE Dp_Unused4_[127];
BYTE DpIntReset; /* 7D80 */
BYTE Dp_Unused5_[127];
};
/*
** The PROM data area on the host (0x7C00), Read Only
*/
struct s_Prom
{
WORD DpSlxCode[2];
WORD DpRev;
WORD Dp_Unused6_;
WORD DpUniq[4];
WORD DpJahre;
WORD DpWoche;
WORD DpHwFeature[5];
WORD DpOemId;
WORD DpSiggy[16];
struct s_Prom {
WORD DpSlxCode[2];
WORD DpRev;
WORD Dp_Unused6_;
WORD DpUniq[4];
WORD DpJahre;
WORD DpWoche;
WORD DpHwFeature[5];
WORD DpOemId;
WORD DpSiggy[16];
};
/*
** Union of the Ctrl and Prom areas
*/
union u_CtrlProm /* This is the control/PROM area (0x7C00) */
{
struct s_Ctrl DpCtrl;
struct s_Prom DpProm;
union u_CtrlProm { /* This is the control/PROM area (0x7C00) */
struct s_Ctrl DpCtrl;
struct s_Prom DpProm;
};
/*
** The top end of memory!
*/
struct s_ParmMapS /* Area containing Parm Map Pointer */
{
BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
WORD DpParmMapAd;
struct s_ParmMapS { /* Area containing Parm Map Pointer */
BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
WORD DpParmMapAd;
};
struct s_StartUpS
{
BYTE Dp_Unused9_[DP_STARTUP_ADDR];
BYTE Dp_LongJump[0x4];
BYTE Dp_Unused10_[2];
BYTE Dp_ShortJump[0x2];
struct s_StartUpS {
BYTE Dp_Unused9_[DP_STARTUP_ADDR];
BYTE Dp_LongJump[0x4];
BYTE Dp_Unused10_[2];
BYTE Dp_ShortJump[0x2];
};
union u_Sram2ParmMap /* This is the top of memory (0x7E00-0x7FFF) */
{
BYTE DpSramMem[DP_SRAM2_SIZE];
union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
BYTE DpSramMem[DP_SRAM2_SIZE];
struct s_ParmMapS DpParmMapS;
struct s_StartUpS DpStartUpS;
};
......@@ -116,13 +110,12 @@ union u_Sram2ParmMap /* This is the top of memory (0x7E00-0x7FFF) */
/*
** This is the DP RAM overlay.
*/
struct DpRam
{
BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
struct DpRam {
BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
};
#define DpControl DpCtrlProm.DpCtrl.DpCtl
......
......@@ -41,7 +41,7 @@
#ifndef lint
#ifdef SCCS
static char *_rio_bootpkt_h_sccs = "@(#)bootpkt.h 1.1" ;
static char *_rio_bootpkt_h_sccs = "@(#)bootpkt.h 1.1";
#endif
#endif
......@@ -49,14 +49,13 @@ static char *_rio_bootpkt_h_sccs = "@(#)bootpkt.h 1.1" ;
* Overlayed onto the Data fields of a regular
* Packet
************************************************/
typedef struct BOOT_PKT BOOT_PKT ;
typedef struct BOOT_PKT BOOT_PKT;
struct BOOT_PKT {
short seq_num ;
char data[10] ;
} ;
short seq_num;
char data[10];
};
#endif
/*********** end of file ***********/
......@@ -97,11 +97,10 @@
#define MAX_RATE B2000
struct baud_rate /* Tag for baud rates */
{
/* short host_rate,*/ /* As passed by the driver */
short divisor, /* The divisor */
prescaler; /* The pre-scaler */
struct baud_rate { /* Tag for baud rates */
/* short host_rate, *//* As passed by the driver */
short divisor, /* The divisor */
prescaler; /* The pre-scaler */
};
#endif
......@@ -21,7 +21,7 @@
#ifndef lint
#ifdef SCCS
static char *_rio_chan_h_sccs = "@(#)chan.h 1.1" ;
static char *_rio_chan_h_sccs = "@(#)chan.h 1.1";
#endif
#endif
......
......@@ -73,20 +73,20 @@
#define TIMER_TICK 0x82
#define STOP_BREAK 0x83
#define BASE(a) ((a) < 4 ? (short*)CIRRUS_FIRST : ((a) < 8 ? (short *)CIRRUS_SECOND : ((a) < 12 ? (short*)CIRRUS_THIRD : (short *)CIRRUS_FOURTH)))
#define txack1 ((short *)0x7104)
#define rxack1 ((short *)0x7102)
#define txack1 ((short *)0x7104)
#define rxack1 ((short *)0x7102)
#define mdack1 ((short *)0x7106)
#define txack2 ((short *)0x7006)
#define rxack2 ((short *)0x7004)
#define mdack2 ((short *)0x7100)
#define txack2 ((short *)0x7006)
#define rxack2 ((short *)0x7004)
#define mdack2 ((short *)0x7100)
#define int_latch ((short *) 0x7800)
#define int_status ((short *) 0x7c00)
#define tx1_pending 0x20
#define rx1_pending 0x10
#define md1_pending 0x40
#define tx2_pending 0x02
#define rx2_pending 0x01
#define md2_pending 0x40
#define int_status ((short *) 0x7c00)
#define tx1_pending 0x20
#define rx1_pending 0x10
#define md1_pending 0x40
#define tx2_pending 0x02
#define rx2_pending 0x01
#define md2_pending 0x40
#define module1_bits 0x07
#define module1_modern 0x08
#define module2_bits 0x70
......@@ -113,65 +113,65 @@
NB. These registers are relative values on 8 bit boundaries whereas
on the RTA's the CIRRUS registers are on word boundaries. Use pointer
arithmetic (short *) to obtain the real addresses required */
#define ccr 0x05 /* Channel Command Register */
#define ier 0x06 /* Interrupt Enable Register */
#define cor1 0x08 /* Channel Option Register 1 */
#define cor2 0x09 /* Channel Option Register 2 */
#define cor3 0x0a /* Channel Option Register 3 */
#define cor4 0x1e /* Channel Option Register 4 */
#define cor5 0x1f /* Channel Option Register 5 */
#define ccsr 0x0b /* Channel Control Status Register */
#define rdcr 0x0e /* Receive Data Count Register */
#define tdcr 0x12 /* Transmit Data Count Register */
#define mcor1 0x15 /* Modem Change Option Register 1 */
#define mcor2 0x16 /* Modem Change Option Regsiter 2 */
#define livr 0x18 /* Local Interrupt Vector Register */
#define schr1 0x1a /* Special Character Register 1 */
#define schr2 0x1b /* Special Character Register 2 */
#define schr3 0x1c /* Special Character Register 3 */
#define schr4 0x1d /* Special Character Register 4 */
#define rtr 0x20 /* Receive Timer Register */
#define rtpr 0x21 /* Receive Timeout Period Register */
#define lnc 0x24 /* Lnext character */
#define rivr 0x43 /* Receive Interrupt Vector Register */
#define tivr 0x42 /* Transmit Interrupt Vector Register */
#define mivr 0x41 /* Modem Interrupt Vector Register */
#define gfrcr 0x40 /* Global Firmware Revision code Reg */
#define ricr 0x44 /* Receive Interrupting Channel Reg */
#define ticr 0x45 /* Transmit Interrupting Channel Reg */
#define micr 0x46 /* Modem Interrupting Channel Register */
#define gcr 0x4b /* Global configuration register*/
#define misr 0x4c /* Modem interrupt status register */
#define ccr 0x05 /* Channel Command Register */
#define ier 0x06 /* Interrupt Enable Register */
#define cor1 0x08 /* Channel Option Register 1 */
#define cor2 0x09 /* Channel Option Register 2 */
#define cor3 0x0a /* Channel Option Register 3 */
#define cor4 0x1e /* Channel Option Register 4 */
#define cor5 0x1f /* Channel Option Register 5 */
#define ccsr 0x0b /* Channel Control Status Register */
#define rdcr 0x0e /* Receive Data Count Register */
#define tdcr 0x12 /* Transmit Data Count Register */
#define mcor1 0x15 /* Modem Change Option Register 1 */
#define mcor2 0x16 /* Modem Change Option Regsiter 2 */
#define livr 0x18 /* Local Interrupt Vector Register */
#define schr1 0x1a /* Special Character Register 1 */
#define schr2 0x1b /* Special Character Register 2 */
#define schr3 0x1c /* Special Character Register 3 */
#define schr4 0x1d /* Special Character Register 4 */
#define rtr 0x20 /* Receive Timer Register */
#define rtpr 0x21 /* Receive Timeout Period Register */
#define lnc 0x24 /* Lnext character */
#define rivr 0x43 /* Receive Interrupt Vector Register */
#define tivr 0x42 /* Transmit Interrupt Vector Register */
#define mivr 0x41 /* Modem Interrupt Vector Register */
#define gfrcr 0x40 /* Global Firmware Revision code Reg */
#define ricr 0x44 /* Receive Interrupting Channel Reg */
#define ticr 0x45 /* Transmit Interrupting Channel Reg */
#define micr 0x46 /* Modem Interrupting Channel Register */
#define gcr 0x4b /* Global configuration register */
#define misr 0x4c /* Modem interrupt status register */
#define rbusr 0x59
#define tbusr 0x5a
#define mbusr 0x5b
#define eoir 0x60 /* End Of Interrupt Register */
#define rdsr 0x62 /* Receive Data / Status Register */
#define tdr 0x63 /* Transmit Data Register */
#define svrr 0x67 /* Service Request Register */
#define eoir 0x60 /* End Of Interrupt Register */
#define rdsr 0x62 /* Receive Data / Status Register */
#define tdr 0x63 /* Transmit Data Register */
#define svrr 0x67 /* Service Request Register */
#define car 0x68 /* Channel Access Register */
#define mir 0x69 /* Modem Interrupt Register */
#define tir 0x6a /* Transmit Interrupt Register */
#define rir 0x6b /* Receive Interrupt Register */
#define msvr1 0x6c /* Modem Signal Value Register 1 */
#define msvr2 0x6d /* Modem Signal Value Register 2*/
#define psvr 0x6f /* Printer Signal Value Register*/
#define car 0x68 /* Channel Access Register */
#define mir 0x69 /* Modem Interrupt Register */
#define tir 0x6a /* Transmit Interrupt Register */
#define rir 0x6b /* Receive Interrupt Register */
#define msvr1 0x6c /* Modem Signal Value Register 1 */
#define msvr2 0x6d /* Modem Signal Value Register 2 */
#define psvr 0x6f /* Printer Signal Value Register */
#define tbpr 0x72 /* Transmit Baud Rate Period Register */
#define tcor 0x76 /* Transmit Clock Option Register */
#define tbpr 0x72 /* Transmit Baud Rate Period Register */
#define tcor 0x76 /* Transmit Clock Option Register */
#define rbpr 0x78 /* Receive Baud Rate Period Register */
#define rber 0x7a /* Receive Baud Rate Extension Register */
#define rcor 0x7c /* Receive Clock Option Register*/
#define ppr 0x7e /* Prescalar Period Register */
#define rbpr 0x78 /* Receive Baud Rate Period Register */
#define rber 0x7a /* Receive Baud Rate Extension Register */
#define rcor 0x7c /* Receive Clock Option Register */
#define ppr 0x7e /* Prescalar Period Register */
/* Misc registers used for forcing the 1400 out of its reset woes */
#define airl 0x6d
......@@ -192,10 +192,10 @@
/* RDSR - when status read from FIFO */
#define RDSR_BREAK 0x08 /* Break received */
#define RDSR_TIMEOUT 0x80 /* No new data timeout */
#define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */
#define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */
#define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */
#define RDSR_TIMEOUT 0x80 /* No new data timeout */
#define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */
#define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */
#define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */
/* PPR */
#define PPR_DEFAULT 0x31 /* Default value - for a 25Mhz clock gives
......@@ -244,7 +244,7 @@
#define IER_TIMEOUT 0x01 /* Timeout on no data */
#define IER_DEFAULT 0x94 /* Default values */
#define IER_PARALLEL 0x84 /* Default for Parallel */
#define IER_PARALLEL 0x84 /* Default for Parallel */
#define IER_EMPTY 0x92 /* Transmitter empty rather than ready */
/* COR1 - Driver only */
......@@ -264,11 +264,11 @@
#define COR1_7BITS 0x02 /* 7 data bits */
#define COR1_8BITS 0x03 /* 8 data bits */
#define COR1_HOST 0xef /* Safe host bits */
#define COR1_HOST 0xef /* Safe host bits */
/* RTA only */
#define COR1_CINPCK 0x00 /* Check parity of received characters */
#define COR1_CNINPCK 0x10 /* Don't check parity */
#define COR1_CINPCK 0x00 /* Check parity of received characters */
#define COR1_CNINPCK 0x10 /* Don't check parity */
/* COR2 bits for both RTA and driver use */
#define COR2_IXANY 0x80 /* IXANY - any character is XON */
......@@ -293,9 +293,9 @@
#define COR3_FCT 0x20 /* Flow control transparency */
#define COR3_SCD12 0x10 /* Special character detect for SCHR's 1 + 2 */
#define COR3_FIFO12 0x0c /* 12 chars for receive FIFO threshold */
#define COR3_FIFO10 0x0a /* 10 chars for receive FIFO threshold */
#define COR3_FIFO8 0x08 /* 8 chars for receive FIFO threshold */
#define COR3_FIFO6 0x06 /* 6 chars for receive FIFO threshold */
#define COR3_FIFO10 0x0a /* 10 chars for receive FIFO threshold */
#define COR3_FIFO8 0x08 /* 8 chars for receive FIFO threshold */
#define COR3_FIFO6 0x06 /* 6 chars for receive FIFO threshold */
#define COR3_THRESHOLD COR3_FIFO8 /* MUST BE LESS THAN MCOR_THRESHOLD */
......@@ -386,7 +386,7 @@
#define MCOR_THRESHBITS 0x0F /* mask for ANDing out the above */
#define MCOR_THRESHOLD MCOR_THRESH9 /* MUST BE GREATER THAN COR3_THRESHOLD */
#define MCOR_THRESHOLD MCOR_THRESH9 /* MUST BE GREATER THAN COR3_THRESHOLD */
/* RTPR */
......@@ -429,25 +429,25 @@
#define CONFIG 0x01 /* Configure a port */
#define MOPEN 0x02 /* Modem open (block for DCD) */
#define CLOSE 0x03 /* Close a port */
#define WFLUSH (0x04 | PRE_EMPTIVE) /* Write flush */
#define RFLUSH (0x05 | PRE_EMPTIVE) /* Read flush */
#define RESUME (0x06 | PRE_EMPTIVE) /* Resume if xoffed */
#define SBREAK 0x07 /* Start break */
#define WFLUSH (0x04 | PRE_EMPTIVE) /* Write flush */
#define RFLUSH (0x05 | PRE_EMPTIVE) /* Read flush */
#define RESUME (0x06 | PRE_EMPTIVE) /* Resume if xoffed */
#define SBREAK 0x07 /* Start break */
#define EBREAK 0x08 /* End break */
#define SUSPEND (0x09 | PRE_EMPTIVE) /* Susp op (behave as tho xoffed) */
#define FCLOSE (0x0a | PRE_EMPTIVE) /* Force close */
#define XPRINT 0x0b /* Xprint packet */
#define MBIS (0x0c | PRE_EMPTIVE) /* Set modem lines */
#define MBIC (0x0d | PRE_EMPTIVE) /* Clear modem lines */
#define MSET (0x0e | PRE_EMPTIVE) /* Set modem lines */
#define SUSPEND (0x09 | PRE_EMPTIVE) /* Susp op (behave as tho xoffed) */
#define FCLOSE (0x0a | PRE_EMPTIVE) /* Force close */
#define XPRINT 0x0b /* Xprint packet */
#define MBIS (0x0c | PRE_EMPTIVE) /* Set modem lines */
#define MBIC (0x0d | PRE_EMPTIVE) /* Clear modem lines */
#define MSET (0x0e | PRE_EMPTIVE) /* Set modem lines */
#define PCLOSE 0x0f /* Pseudo close - Leaves rx/tx enabled */
#define MGET (0x10 | PRE_EMPTIVE) /* Force update of modem status */
#define MEMDUMP (0x11 | PRE_EMPTIVE) /* Send back mem from addr supplied */
#define READ_REGISTER (0x12 | PRE_EMPTIVE) /* Read CD1400 register (debug) */
#define MGET (0x10 | PRE_EMPTIVE) /* Force update of modem status */
#define MEMDUMP (0x11 | PRE_EMPTIVE) /* Send back mem from addr supplied */
#define READ_REGISTER (0x12 | PRE_EMPTIVE) /* Read CD1400 register (debug) */
/* "Command" packets going from remote to host COMPLETE and MODEM_STATUS
use data[4] / data[3] to indicate current state and modem status respectively
*/
*/
#define COMPLETE (0x20 | PRE_EMPTIVE)
/* Command complete */
......
......@@ -42,7 +42,7 @@
#ifndef lint
#ifdef SCCS
static char *_rio_cmd_h_sccs = "@(#)cmd.h 1.1" ;
static char *_rio_cmd_h_sccs = "@(#)cmd.h 1.1";
#endif
#endif
......@@ -52,7 +52,7 @@ static char *_rio_cmd_h_sccs = "@(#)cmd.h 1.1" ;
#define CMD_IGNORE_PKT ( (ushort) 0)
#define CMD_STATUS_REQ ( (ushort) 1)
#define CMD_UNIT_STATUS_REQ ( (ushort) 2) /* Is this needed ??? */
#define CMD_UNIT_STATUS_REQ ( (ushort) 2) /* Is this needed ??? */
#define CMD_CONF_PORT ( (ushort) 3)
#define CMD_CONF_UNIT ( (ushort) 4)
#define CMD_ROUTE_MAP_REQ ( (ushort) 5)
......@@ -81,4 +81,3 @@ static char *_rio_cmd_h_sccs = "@(#)cmd.h 1.1" ;
#endif
/*********** end of file ***********/
......@@ -44,16 +44,15 @@ static char *_cmdblk_h_sccs_ = "@(#)cmdblk.h 1.2";
** a rup.
*/
struct CmdBlk
{
struct CmdBlk *NextP; /* Pointer to next command block */
struct PKT Packet; /* A packet, to copy to the rup */
/* The func to call to check if OK */
int (*PreFuncP)(int, struct CmdBlk *);
int PreArg; /* The arg for the func */
/* The func to call when completed */
int (*PostFuncP)(int, struct CmdBlk *);
int PostArg; /* The arg for the func */
struct CmdBlk {
struct CmdBlk *NextP; /* Pointer to next command block */
struct PKT Packet; /* A packet, to copy to the rup */
/* The func to call to check if OK */
int (*PreFuncP) (int, struct CmdBlk *);
int PreArg; /* The arg for the func */
/* The func to call when completed */
int (*PostFuncP) (int, struct CmdBlk *);
int PostArg; /* The arg for the func */
};
#define NUM_RIO_CMD_BLKS (3 * (MAX_RUP * 4 + LINKS_PER_UNIT * 4))
......
......@@ -54,135 +54,112 @@ static char *_cmdpkt_h_sccs_ = "@(#)cmdpkt.h 1.2";
** This structure overlays a PktCmd->CmdData structure, and so starts
** at Data[2] in the actual pkt!
*/
struct BootSequence
{
WORD NumPackets;
WORD LoadBase;
WORD CodeSize;
struct BootSequence {
WORD NumPackets;
WORD LoadBase;
WORD CodeSize;
};
#define BOOT_SEQUENCE_LEN 8
struct SamTop
{
BYTE Unit;
BYTE Link;
struct SamTop {
BYTE Unit;
BYTE Link;
};
struct CmdHdr
{
BYTE PcCommand;
union
{
BYTE PcPhbNum;
BYTE PcLinkNum;
BYTE PcIDNum;
} U0;
struct CmdHdr {
BYTE PcCommand;
union {
BYTE PcPhbNum;
BYTE PcLinkNum;
BYTE PcIDNum;
} U0;
};
struct PktCmd
{
union
{
struct
{
struct CmdHdr CmdHdr;
struct BootSequence PcBootSequence;
} S1;
struct
{
WORD PcSequence;
BYTE PcBootData[RTA_BOOT_DATA_SIZE];
} S2;
struct
{
WORD __crud__;
BYTE PcUniqNum[4]; /* this is really a uint. */
BYTE PcModuleTypes; /* what modules are fitted */
} S3;
struct
{
struct CmdHdr CmdHdr;
BYTE __undefined__;
BYTE PcModemStatus;
BYTE PcPortStatus;
BYTE PcSubCommand; /* commands like mem or register dump */
WORD PcSubAddr; /* Address for command */
BYTE PcSubData[64]; /* Date area for command */
} S4;
struct
{
struct CmdHdr CmdHdr;
BYTE PcCommandText[1];
BYTE __crud__[20];
BYTE PcIDNum2; /* It had to go somewhere! */
} S5;
struct
{
struct CmdHdr CmdHdr;
struct SamTop Topology[LINKS_PER_UNIT];
} S6;
} U1;
struct PktCmd {
union {
struct {
struct CmdHdr CmdHdr;
struct BootSequence PcBootSequence;
} S1;
struct {
WORD PcSequence;
BYTE PcBootData[RTA_BOOT_DATA_SIZE];
} S2;
struct {
WORD __crud__;
BYTE PcUniqNum[4]; /* this is really a uint. */
BYTE PcModuleTypes; /* what modules are fitted */
} S3;
struct {
struct CmdHdr CmdHdr;
BYTE __undefined__;
BYTE PcModemStatus;
BYTE PcPortStatus;
BYTE PcSubCommand; /* commands like mem or register dump */
WORD PcSubAddr; /* Address for command */
BYTE PcSubData[64]; /* Date area for command */
} S4;
struct {
struct CmdHdr CmdHdr;
BYTE PcCommandText[1];
BYTE __crud__[20];
BYTE PcIDNum2; /* It had to go somewhere! */
} S5;
struct {
struct CmdHdr CmdHdr;
struct SamTop Topology[LINKS_PER_UNIT];
} S6;
} U1;
};
struct PktCmd_M
{
union
{
struct
{
struct
{
uchar PcCommand;
union
{
uchar PcPhbNum;
uchar PcLinkNum;
uchar PcIDNum;
} U0;
} CmdHdr;
struct
{
ushort NumPackets;
ushort LoadBase;
ushort CodeSize;
} PcBootSequence;
} S1;
struct
{
ushort PcSequence;
uchar PcBootData[RTA_BOOT_DATA_SIZE];
} S2;
struct
{
ushort __crud__;
uchar PcUniqNum[4]; /* this is really a uint. */
uchar PcModuleTypes; /* what modules are fitted */
} S3;
struct
{
ushort __cmd_hdr__;
uchar __undefined__;
uchar PcModemStatus;
uchar PcPortStatus;
uchar PcSubCommand;
ushort PcSubAddr;