Commit 965c7eca authored by Ingo Molnar's avatar Ingo Molnar
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x86: remove the Voyager 32-bit subarch



Impact: remove unused/broken code

The Voyager subarch last built successfully on the v2.6.26 kernel
and has been stale since then and does not build on the v2.6.27,
v2.6.28 and v2.6.29-rc5 kernels.

No actual users beyond the maintainer reported this breakage.
Patches were sent and most of the fixes were accepted but the
discussion around how to do a few remaining issues cleanly
fizzled out with no resolution and the code remained broken.

In the v2.6.30 x86 tree development cycle 32-bit subarch support
has been reworked and removed - and the Voyager code, beyond the
build problems already known, needs serious and significant
changes and probably a rewrite to support it.

CONFIG_X86_VOYAGER has been marked BROKEN then. The maintainer has
been notified but no patches have been sent so far to fix it.

While all other subarchs have been converted to the new scheme,
voyager is still broken. We'd prefer to receive patches which
clean up the current situation in a constructive way, but even in
case of removal there is no obstacle to add that support back
after the issues have been sorted out in a mutually acceptable
fashion.

So remove this inactive code for now.
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 8425091f
......@@ -302,7 +302,6 @@ config X86_EXTENDED_PLATFORM
SGI 320/540 (Visual Workstation)
Summit/EXA (IBM x440)
Unisys ES7000 IA32 series
Voyager (NCR)
If you have one of these systems, or if you want to build a
generic distribution kernel, say Y here - otherwise say N.
......@@ -423,19 +422,6 @@ config X86_ES7000
Support for Unisys ES7000 systems. Say 'Y' here if this kernel is
supposed to run on an IA32-based Unisys ES7000 system.
config X86_VOYAGER
bool "Voyager (NCR)"
depends on SMP && !PCI && BROKEN
depends on X86_32_NON_STANDARD
---help---
Voyager is an MCA-based 32-way capable SMP architecture proprietary
to NCR Corp. Machine classes 345x/35xx/4100/51xx are Voyager-based.
*** WARNING ***
If you do not specifically know you have a Voyager based machine,
say N here, otherwise the kernel you build will not be bootable.
config SCHED_OMIT_FRAME_POINTER
def_bool y
prompt "Single-depth WCHAN output"
......
......@@ -32,7 +32,6 @@ setup-y += a20.o cmdline.o copy.o cpu.o cpucheck.o edd.o
setup-y += header.o main.o mca.o memory.o pm.o pmjump.o
setup-y += printf.o string.o tty.o video.o video-mode.o version.o
setup-$(CONFIG_X86_APM_BOOT) += apm.o
setup-$(CONFIG_X86_VOYAGER) += voyager.o
# The link order of the video-*.o modules can matter. In particular,
# video-vga.o *must* be listed first, followed by video-vesa.o.
......
......@@ -126,11 +126,6 @@ static void enable_a20_fast(void)
int enable_a20(void)
{
#ifdef CONFIG_X86_VOYAGER
/* On Voyager, a20_test() is unsafe? */
enable_a20_kbc();
return 0;
#else
int loops = A20_ENABLE_LOOPS;
int kbc_err;
......@@ -164,5 +159,4 @@ int enable_a20(void)
}
return -1;
#endif
}
......@@ -302,9 +302,6 @@ void probe_cards(int unsafe);
/* video-vesa.c */
void vesa_store_edid(void);
/* voyager.c */
int query_voyager(void);
#endif /* __ASSEMBLY__ */
#endif /* BOOT_BOOT_H */
......@@ -149,11 +149,6 @@ void main(void)
/* Query MCA information */
query_mca();
/* Voyager */
#ifdef CONFIG_X86_VOYAGER
query_voyager();
#endif
/* Query Intel SpeedStep (IST) information */
query_ist();
......
/* -*- linux-c -*- ------------------------------------------------------- *
*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright 2007 rPath, Inc. - All Rights Reserved
*
* This file is part of the Linux kernel, and is made available under
* the terms of the GNU General Public License version 2.
*
* ----------------------------------------------------------------------- */
/*
* Get the Voyager config information
*/
#include "boot.h"
int query_voyager(void)
{
u8 err;
u16 es, di;
/* Abuse the apm_bios_info area for this */
u8 *data_ptr = (u8 *)&boot_params.apm_bios_info;
data_ptr[0] = 0xff; /* Flag on config not found(?) */
asm("pushw %%es ; "
"int $0x15 ; "
"setc %0 ; "
"movw %%es, %1 ; "
"popw %%es"
: "=q" (err), "=r" (es), "=D" (di)
: "a" (0xffc0));
if (err)
return -1; /* Not Voyager */
set_fs(es);
copy_from_fs(data_ptr, di, 7); /* Table is 7 bytes apparently */
return 0;
}
......@@ -197,7 +197,6 @@ CONFIG_SPARSE_IRQ=y
CONFIG_X86_FIND_SMP_CONFIG=y
CONFIG_X86_MPPARSE=y
# CONFIG_X86_ELAN is not set
# CONFIG_X86_VOYAGER is not set
# CONFIG_X86_GENERICARCH is not set
# CONFIG_X86_VSMP is not set
# CONFIG_X86_RDC321X is not set
......
......@@ -199,7 +199,6 @@ CONFIG_SPARSE_IRQ=y
CONFIG_X86_FIND_SMP_CONFIG=y
CONFIG_X86_MPPARSE=y
# CONFIG_X86_ELAN is not set
# CONFIG_X86_VOYAGER is not set
# CONFIG_X86_GENERICARCH is not set
# CONFIG_X86_VSMP is not set
CONFIG_SCHED_OMIT_FRAME_POINTER=y
......
/* defines for inline arch setup functions */
#include <linux/clockchips.h>
#include <asm/voyager.h>
#include <asm/i8253.h>
/**
* do_timer_interrupt_hook - hook into timer tick
*
* Call the pit clock event handler. see asm/i8253.h
**/
static inline void do_timer_interrupt_hook(void)
{
global_clock_event->event_handler(global_clock_event);
voyager_timer_interrupt();
}
/* -*- mode: c; c-basic-offset: 8 -*- */
/* Copyright (C) 2002
*
* Author: James.Bottomley@HansenPartnership.com
*
* linux/arch/i386/voyager/entry_arch.h
*
* This file builds the VIC and QIC CPI gates
*/
/* initialise the voyager interrupt gates
*
* This uses the macros in irq.h to set up assembly jump gates. The
* calls are then redirected to the same routine with smp_ prefixed */
BUILD_INTERRUPT(vic_sys_interrupt, VIC_SYS_INT)
BUILD_INTERRUPT(vic_cmn_interrupt, VIC_CMN_INT)
BUILD_INTERRUPT(vic_cpi_interrupt, VIC_CPI_LEVEL0);
/* do all the QIC interrupts */
BUILD_INTERRUPT(qic_timer_interrupt, QIC_TIMER_CPI);
BUILD_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI);
BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI);
BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI);
BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI);
BUILD_INTERRUPT(qic_call_function_single_interrupt, QIC_CALL_FUNCTION_SINGLE_CPI);
#include <asm/voyager.h>
#include <asm/setup.h>
#define VOYAGER_BIOS_INFO ((struct voyager_bios_info *) \
(&boot_params.apm_bios_info))
/* Hook to call BIOS initialisation function */
/* for voyager, pass the voyager BIOS/SUS info area to the detection
* routines */
#define ARCH_SETUP voyager_detect(VOYAGER_BIOS_INFO);
/* Copyright (C) 1999,2001
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
* Standard include definitions for the NCR Voyager Interrupt Controller */
/* The eight CPI vectors. To activate a CPI, you write a bit mask
* corresponding to the processor set to be interrupted into the
* relevant register. That set of CPUs will then be interrupted with
* the CPI */
static const int VIC_CPI_Registers[] =
{0xFC00, 0xFC01, 0xFC08, 0xFC09,
0xFC10, 0xFC11, 0xFC18, 0xFC19 };
#define VIC_PROC_WHO_AM_I 0xfc29
# define QUAD_IDENTIFIER 0xC0
# define EIGHT_SLOT_IDENTIFIER 0xE0
#define QIC_EXTENDED_PROCESSOR_SELECT 0xFC72
#define VIC_CPI_BASE_REGISTER 0xFC41
#define VIC_PROCESSOR_ID 0xFC21
# define VIC_CPU_MASQUERADE_ENABLE 0x8
#define VIC_CLAIM_REGISTER_0 0xFC38
#define VIC_CLAIM_REGISTER_1 0xFC39
#define VIC_REDIRECT_REGISTER_0 0xFC60
#define VIC_REDIRECT_REGISTER_1 0xFC61
#define VIC_PRIORITY_REGISTER 0xFC20
#define VIC_PRIMARY_MC_BASE 0xFC48
#define VIC_SECONDARY_MC_BASE 0xFC49
#define QIC_PROCESSOR_ID 0xFC71
# define QIC_CPUID_ENABLE 0x08
#define QIC_VIC_CPI_BASE_REGISTER 0xFC79
#define QIC_CPI_BASE_REGISTER 0xFC7A
#define QIC_MASK_REGISTER0 0xFC80
/* NOTE: these are masked high, enabled low */
# define QIC_PERF_TIMER 0x01
# define QIC_LPE 0x02
# define QIC_SYS_INT 0x04
# define QIC_CMN_INT 0x08
/* at the moment, just enable CMN_INT, disable SYS_INT */
# define QIC_DEFAULT_MASK0 (~(QIC_CMN_INT /* | VIC_SYS_INT */))
#define QIC_MASK_REGISTER1 0xFC81
# define QIC_BOOT_CPI_MASK 0xFE
/* Enable CPI's 1-6 inclusive */
# define QIC_CPI_ENABLE 0x81
#define QIC_INTERRUPT_CLEAR0 0xFC8A
#define QIC_INTERRUPT_CLEAR1 0xFC8B
/* this is where we place the CPI vectors */
#define VIC_DEFAULT_CPI_BASE 0xC0
/* this is where we place the QIC CPI vectors */
#define QIC_DEFAULT_CPI_BASE 0xD0
#define VIC_BOOT_INTERRUPT_MASK 0xfe
extern void smp_vic_timer_interrupt(void);
/* Copyright (C) 1999,2001
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
* Standard include definitions for the NCR Voyager system */
#undef VOYAGER_DEBUG
#undef VOYAGER_CAT_DEBUG
#ifdef VOYAGER_DEBUG
#define VDEBUG(x) printk x
#else
#define VDEBUG(x)
#endif
/* There are three levels of voyager machine: 3,4 and 5. The rule is
* if it's less than 3435 it's a Level 3 except for a 3360 which is
* a level 4. A 3435 or above is a Level 5 */
#define VOYAGER_LEVEL5_AND_ABOVE 0x3435
#define VOYAGER_LEVEL4 0x3360
/* The L4 DINO ASIC */
#define VOYAGER_DINO 0x43
/* voyager ports in standard I/O space */
#define VOYAGER_MC_SETUP 0x96
#define VOYAGER_CAT_CONFIG_PORT 0x97
# define VOYAGER_CAT_DESELECT 0xff
#define VOYAGER_SSPB_RELOCATION_PORT 0x98
/* Valid CAT controller commands */
/* start instruction register cycle */
#define VOYAGER_CAT_IRCYC 0x01
/* start data register cycle */
#define VOYAGER_CAT_DRCYC 0x02
/* move to execute state */
#define VOYAGER_CAT_RUN 0x0F
/* end operation */
#define VOYAGER_CAT_END 0x80
/* hold in idle state */
#define VOYAGER_CAT_HOLD 0x90
/* single step an "intest" vector */
#define VOYAGER_CAT_STEP 0xE0
/* return cat controller to CLEMSON mode */
#define VOYAGER_CAT_CLEMSON 0xFF
/* the default cat command header */
#define VOYAGER_CAT_HEADER 0x7F
/* the range of possible CAT module ids in the system */
#define VOYAGER_MIN_MODULE 0x10
#define VOYAGER_MAX_MODULE 0x1f
/* The voyager registers per asic */
#define VOYAGER_ASIC_ID_REG 0x00
#define VOYAGER_ASIC_TYPE_REG 0x01
/* the sub address registers can be made auto incrementing on reads */
#define VOYAGER_AUTO_INC_REG 0x02
# define VOYAGER_AUTO_INC 0x04
# define VOYAGER_NO_AUTO_INC 0xfb
#define VOYAGER_SUBADDRDATA 0x03
#define VOYAGER_SCANPATH 0x05
# define VOYAGER_CONNECT_ASIC 0x01
# define VOYAGER_DISCONNECT_ASIC 0xfe
#define VOYAGER_SUBADDRLO 0x06
#define VOYAGER_SUBADDRHI 0x07
#define VOYAGER_SUBMODSELECT 0x08
#define VOYAGER_SUBMODPRESENT 0x09
#define VOYAGER_SUBADDR_LO 0xff
#define VOYAGER_SUBADDR_HI 0xffff
/* the maximum size of a scan path -- used to form instructions */
#define VOYAGER_MAX_SCAN_PATH 0x100
/* the biggest possible register size (in bytes) */
#define VOYAGER_MAX_REG_SIZE 4
/* Total number of possible modules (including submodules) */
#define VOYAGER_MAX_MODULES 16
/* Largest number of asics per module */
#define VOYAGER_MAX_ASICS_PER_MODULE 7
/* the CAT asic of each module is always the first one */
#define VOYAGER_CAT_ID 0
#define VOYAGER_PSI 0x1a
/* voyager instruction operations and registers */
#define VOYAGER_READ_CONFIG 0x1
#define VOYAGER_WRITE_CONFIG 0x2
#define VOYAGER_BYPASS 0xff
typedef struct voyager_asic {
__u8 asic_addr; /* ASIC address; Level 4 */
__u8 asic_type; /* ASIC type */
__u8 asic_id; /* ASIC id */
__u8 jtag_id[4]; /* JTAG id */
__u8 asic_location; /* Location within scan path; start w/ 0 */
__u8 bit_location; /* Location within bit stream; start w/ 0 */
__u8 ireg_length; /* Instruction register length */
__u16 subaddr; /* Amount of sub address space */
struct voyager_asic *next; /* Next asic in linked list */
} voyager_asic_t;
typedef struct voyager_module {
__u8 module_addr; /* Module address */
__u8 scan_path_connected; /* Scan path connected */
__u16 ee_size; /* Size of the EEPROM */
__u16 num_asics; /* Number of Asics */
__u16 inst_bits; /* Instruction bits in the scan path */
__u16 largest_reg; /* Largest register in the scan path */
__u16 smallest_reg; /* Smallest register in the scan path */
voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */
struct voyager_module *submodule; /* Submodule pointer */
struct voyager_module *next; /* Next module in linked list */
} voyager_module_t;
typedef struct voyager_eeprom_hdr {
__u8 module_id[4];
__u8 version_id;
__u8 config_id;
__u16 boundry_id; /* boundary scan id */
__u16 ee_size; /* size of EEPROM */
__u8 assembly[11]; /* assembly # */
__u8 assembly_rev; /* assembly rev */
__u8 tracer[4]; /* tracer number */
__u16 assembly_cksum; /* asm checksum */
__u16 power_consump; /* pwr requirements */
__u16 num_asics; /* number of asics */
__u16 bist_time; /* min. bist time */
__u16 err_log_offset; /* error log offset */
__u16 scan_path_offset;/* scan path offset */
__u16 cct_offset;
__u16 log_length; /* length of err log */
__u16 xsum_end; /* offset to end of
checksum */
__u8 reserved[4];
__u8 sflag; /* starting sentinal */
__u8 part_number[13]; /* prom part number */
__u8 version[10]; /* version number */
__u8 signature[8];
__u16 eeprom_chksum;
__u32 data_stamp_offset;
__u8 eflag ; /* ending sentinal */
} __attribute__((packed)) voyager_eprom_hdr_t;
#define VOYAGER_EPROM_SIZE_OFFSET \
((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size)))
#define VOYAGER_XSUM_END_OFFSET 0x2a
/* the following three definitions are for internal table layouts
* in the module EPROMs. We really only care about the IDs and
* offsets */
typedef struct voyager_sp_table {
__u8 asic_id;
__u8 bypass_flag;
__u16 asic_data_offset;
__u16 config_data_offset;
} __attribute__((packed)) voyager_sp_table_t;
typedef struct voyager_jtag_table {
__u8 icode[4];
__u8 runbist[4];
__u8 intest[4];
__u8 samp_preld[4];
__u8 ireg_len;
} __attribute__((packed)) voyager_jtt_t;
typedef struct voyager_asic_data_table {
__u8 jtag_id[4];
__u16 length_bsr;
__u16 length_bist_reg;
__u32 bist_clk;
__u16 subaddr_bits;
__u16 seed_bits;
__u16 sig_bits;
__u16 jtag_offset;
} __attribute__((packed)) voyager_at_t;
/* Voyager Interrupt Controller (VIC) registers */
/* Base to add to Cross Processor Interrupts (CPIs) when triggering
* the CPU IRQ line */
/* register defines for the WCBICs (one per processor) */
#define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */
#define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */
#define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */
#define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */
#define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */
#define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */
#define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */
#define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */
/* top of memory registers */
#define VOYAGER_WCBIC_TOM_L 0x4
#define VOYAGER_WCBIC_TOM_H 0x5
/* register defines for Voyager Memory Contol (VMC)
* these are present on L4 machines only */
#define VOYAGER_VMC1 0x81
#define VOYAGER_VMC2 0x91
#define VOYAGER_VMC3 0xa1
#define VOYAGER_VMC4 0xb1
/* VMC Ports */
#define VOYAGER_VMC_MEMORY_SETUP 0x9
# define VMC_Interleaving 0x01
# define VMC_4Way 0x02
# define VMC_EvenCacheLines 0x04
# define VMC_HighLine 0x08
# define VMC_Start0_Enable 0x20
# define VMC_Start1_Enable 0x40
# define VMC_Vremap 0x80
#define VOYAGER_VMC_BANK_DENSITY 0xa
# define VMC_BANK_EMPTY 0
# define VMC_BANK_4MB 1
# define VMC_BANK_16MB 2
# define VMC_BANK_64MB 3
# define VMC_BANK0_MASK 0x03
# define VMC_BANK1_MASK 0x0C
# define VMC_BANK2_MASK 0x30
# define VMC_BANK3_MASK 0xC0
/* Magellan Memory Controller (MMC) defines - present on L5 */
#define VOYAGER_MMC_ASIC_ID 1
/* the two memory modules corresponding to memory cards in the system */
#define VOYAGER_MMC_MEMORY0_MODULE 0x14
#define VOYAGER_MMC_MEMORY1_MODULE 0x15
/* the Magellan Memory Address (MMA) defines */
#define VOYAGER_MMA_ASIC_ID 2
/* Submodule number for the Quad Baseboard */
#define VOYAGER_QUAD_BASEBOARD 1
/* ASIC defines for the Quad Baseboard */
#define VOYAGER_QUAD_QDATA0 1
#define VOYAGER_QUAD_QDATA1 2
#define VOYAGER_QUAD_QABC 3
/* Useful areas in extended CMOS */
#define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a
#define VOYAGER_MEMORY_CLICKMAP 0xa23
#define VOYAGER_DUMP_LOCATION 0xb1a
/* SUS In Control bit - used to tell SUS that we don't need to be
* babysat anymore */
#define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff
# define VOYAGER_IN_CONTROL_FLAG 0x80
/* Voyager PSI defines */
#define VOYAGER_PSI_STATUS_REG 0x08
# define PSI_DC_FAIL 0x01
# define PSI_MON 0x02
# define PSI_FAULT 0x04
# define PSI_ALARM 0x08
# define PSI_CURRENT 0x10
# define PSI_DVM 0x20
# define PSI_PSCFAULT 0x40
# define PSI_STAT_CHG 0x80
#define VOYAGER_PSI_SUPPLY_REG 0x8000
/* read */
# define PSI_FAIL_DC 0x01
# define PSI_FAIL_AC 0x02
# define PSI_MON_INT 0x04
# define PSI_SWITCH_OFF 0x08
# define PSI_HX_OFF 0x10
# define PSI_SECURITY 0x20
# define PSI_CMOS_BATT_LOW 0x40
# define PSI_CMOS_BATT_FAIL 0x80
/* write */
# define PSI_CLR_SWITCH_OFF 0x13
# define PSI_CLR_HX_OFF 0x14
# define PSI_CLR_CMOS_BATT_FAIL 0x17
#define VOYAGER_PSI_MASK 0x8001
# define PSI_MASK_MASK 0x10
#define VOYAGER_PSI_AC_FAIL_REG 0x8004
#define AC_FAIL_STAT_CHANGE 0x80
#define VOYAGER_PSI_GENERAL_REG 0x8007
/* read */
# define PSI_SWITCH_ON 0x01
# define PSI_SWITCH_ENABLED 0x02
# define PSI_ALARM_ENABLED 0x08
# define PSI_SECURE_ENABLED 0x10
# define PSI_COLD_RESET 0x20
# define PSI_COLD_START 0x80
/* write */
# define PSI_POWER_DOWN 0x10
# define PSI_SWITCH_DISABLE 0x01
# define PSI_SWITCH_ENABLE 0x11
# define PSI_CLEAR 0x12
# define PSI_ALARM_DISABLE 0x03
# define PSI_ALARM_ENABLE 0x13
# define PSI_CLEAR_COLD_RESET 0x05
# define PSI_SET_COLD_RESET 0x15
# define PSI_CLEAR_COLD_START 0x07
# define PSI_SET_COLD_START 0x17
struct voyager_bios_info {
__u8 len;
__u8 major;
__u8 minor;
__u8 debug;
__u8 num_classes;
__u8 class_1;
__u8 class_2;
};
/* The following structures and definitions are for the Kernel/SUS
* interface these are needed to find out how SUS initialised any Quad
* boards in the system */
#define NUMBER_OF_MC_BUSSES 2
#define SLOTS_PER_MC_BUS 8
#define MAX_CPUS 16 /* 16 way CPU system */
#define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */
#define MAX_CACHE_LEVELS 4 /* # of cache levels supported */
#define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */
#define NUMBER_OF_POS_REGS 8
typedef struct {
__u8 MC_Slot;
__u8 POS_Values[NUMBER_OF_POS_REGS];
} __attribute__((packed)) MC_SlotInformation_t;
struct QuadDescription {
__u8 Type; /* for type 0 (DYADIC or MONADIC) all fields
* will be zero except for slot */
__u8 StructureVersion;
__u32 CPI_BaseAddress;
__u32 LARC_BankSize;
__u32 LocalMemoryStateBits;
__u8 Slot; /* Processor slots 1 - 4 */
} __attribute__((packed));
struct ProcBoardInfo {
__u8 Type;
__u8 StructureVersion;
__u8 NumberOfBoards;
struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS];
} __attribute__((packed));
struct CacheDescription {
__u8 Level;
__u32 TotalSize;
__u16 LineSize;
__u8 Associativity;
__u8 CacheType;
__u8 WriteType;
__u8 Number_CPUs_SharedBy;
__u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS];
} __attribute__((packed));
struct CPU_Description {
__u8 CPU_HardwareId;
char *FRU_String;
__u8 NumberOfCacheLevels;
struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS];
} __attribute__((packed));
struct CPU_Info {
__u8 Type;
__u8 StructureVersion;
__u8 NumberOf_CPUs;
struct CPU_Description CPU_Data[MAX_CPUS];
} __attribute__((packed));