Commit a2a9a614 authored by Philippe Gerum's avatar Philippe Gerum
Browse files

arm/ipipe: l2x0: force enable write-allocate for L310 rev >= r3p2

Since revision r3p2, disabling write-allocate as a hack to reduce
latencies causes random cache coherence issues on SMP.

In such hardware configuration, we have to stick to the letter of the
ARM architecture specification, and keep WA enabled.
parent 70473e41
......@@ -815,6 +815,11 @@ static int __init __l2c_init(const struct l2c_init_data *data,
switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
case L2X0_CACHE_ID_PART_L310:
if ((cache_id & L2X0_CACHE_ID_RTL_MASK)
>= L310_CACHE_ID_RTL_R3P2) {
l2x0_wa = 1;
pr_alert("L2C: I-pipe: revision >= L310-r3p2 detected, forcing WA.\n");
case L2X0_CACHE_ID_PART_L220:
if (l2x0_wa < 0) {
l2x0_wa = 0;
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