Commit c5aec4c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Ben Herrenschmidt:
 "Here is the bulk of the powerpc changes for this merge window.  It got
  a bit delayed in part because I wasn't paying attention, and in part
  because I discovered I had a core PCI change without a PCI maintainer
  ack in it.  Bjorn eventually agreed it was ok to merge it though we'll
  probably improve it later and I didn't want to rebase to add his ack.

  There is going to be a bit more next week, essentially fixes that I
  still want to sort through and test.

  The biggest item this time is the support to build the ppc64 LE kernel
  with our new v2 ABI.  We previously supported v2 userspace but the
  kernel itself was a tougher nut to crack.  This is now sorted mostly
  thanks to Anton and Rusty.

  We also have a fairly big series from Cedric that add support for
  64-bit LE zImage boot wrapper.  This was made harder by the fact that
  traditionally our zImage wrapper was always 32-bit, but our new LE
  toolchains don't really support 32-bit anymore (it's somewhat there
  but not really "supported") so we didn't want to rely on it.  This
  meant more churn that just endian fixes.

  This brings some more LE bits as well, such as the ability to run in
  LE mode without a hypervisor (ie. under OPAL firmware) by doing the
  right OPAL call to reinitialize the CPU to take HV interrupts in the
  right mode and the usual pile of endian fixes.

  There's another series from Gavin adding EEH improvements (one day we
  *will* have a release with less than 20 EEH patches, I promise!).

  Another highlight is the support for the "Split core" functionality on
  P8 by Michael.  This allows a P8 core to be split into "sub cores" of
  4 threads which allows the subcores to run different guests under KVM
  (the HW still doesn't support a partition per thread).

  And then the usual misc bits and fixes ..."

[ Further delayed by gmail deciding that BenH is a dirty spammer.
  Google knows.  ]

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits)
  powerpc/powernv: Add missing include to LPC code
  selftests/powerpc: Test the THP bug we fixed in the previous commit
  powerpc/mm: Check paca psize is up to date for huge mappings
  powerpc/powernv: Pass buffer size to OPAL validate flash call
  powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC()
  powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC()
  powerpc/powernv: Set memory_block_size_bytes to 256MB
  powerpc: Allow ppc_md platform hook to override memory_block_size_bytes
  powerpc/powernv: Fix endian issues in memory error handling code
  powerpc/eeh: Skip eeh sysfs when eeh is disabled
  powerpc: 64bit sendfile is capped at 2GB
  powerpc/powernv: Provide debugfs access to the LPC bus via OPAL
  powerpc/serial: Use saner flags when creating legacy ports
  powerpc: Add cpu family documentation
  powerpc/xmon: Fix up xmon format strings
  powerpc/powernv: Add calls to support little endian host
  powerpc: Document sysfs DSCR interface
  powerpc: Fix regression of per-CPU DSCR setting
  powerpc: Split __SYSFS_SPRSETUP macro
  arch: powerpc/fadump: Cleaning up inconsistent NULL checks
  ...
parents 2937f5ef 0c0a3e5a
What: /sys/devices/system/cpu/dscr_default
Date: 13-May-2014
KernelVersion: v3.15.0
Contact:
Description: Writes are equivalent to writing to
/sys/devices/system/cpu/cpuN/dscr on all CPUs.
Reads return the last written value or 0.
This value is not a global default: it is a way to set
all per-CPU defaults at the same time.
Values: 64 bit unsigned integer (bit field)
What: /sys/devices/system/cpu/cpu[0-9]+/dscr
Date: 13-May-2014
KernelVersion: v3.15.0
Contact:
Description: Default value for the Data Stream Control Register (DSCR) on
a CPU.
This default value is used when the kernel is executing and
for any process that has not set the DSCR itself.
If a process ever sets the DSCR (via direct access to the
SPR) that value will be persisted for that process and used
on any CPU where it executes (overriding the value described
here).
If set by a process it will be inherited by child processes.
Values: 64 bit unsigned integer (bit field)
......@@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240, b4860, t1040
1. Clock Block Binding
Required properties:
......@@ -85,7 +93,7 @@ Example for clock block and clock provider:
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
}
};
pll0: pll0@800 {
#clock-cells = <1>;
......
KEYMILE bfticu Chassis Management FPGA
The bfticu is a multifunction device that manages the whole chassis.
Its main functionality is to collect IRQs from the whole chassis and signals
them to a single controller.
Required properties:
- compatible: "keymile,bfticu"
- interrupt-controller: the bfticu FPGA is an interrupt controller
- interrupts: the main IRQ line to signal the collected IRQs
- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to
- reg: access on the parent local bus (chip select, offset in chip select, size)
Example:
chassis-mgmt@3,0 {
compatible = "keymile,bfticu";
interrupt-controller;
#interrupt-cells = <2>;
reg = <3 0 0x100>;
interrupt-parent = <&mpic>;
interrupts = <6 1 0 0>;
};
KEYMILE qrio Board Control CPLD
The qrio is a multifunction device that controls the KEYMILE boards based on
the kmp204x design.
It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable
GPIO blocks.
Required properties:
- compatible: "keymile,qriox"
- reg: access on the parent local bus (chip select, offset in chip select, size)
Example:
board-control@1,0 {
compatible = "keymile,qriox";
reg = <1 0 0x80>;
};
IBM Akebono board device tree
=============================
The IBM Akebono board is a development board for the PPC476GTR SoC.
0) The root node
Required properties:
- model : "ibm,akebono".
- compatible : "ibm,akebono" , "ibm,476gtr".
1.a) The Secure Digital Host Controller Interface (SDHCI) node
Represent the Secure Digital Host Controller Interfaces.
Required properties:
- compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
- reg : should contain the SDHCI registers location and length.
- interrupt-parent : a phandle for the interrupt controller.
- interrupts : should contain the SDHCI interrupt.
1.b) The Advanced Host Controller Interface (AHCI) SATA node
Represents the advanced host controller SATA interface.
Required properties:
- compatible : should be "ibm,476gtr-ahci".
- reg : should contain the AHCI registers location and length.
- interrupt-parent : a phandle for the interrupt controller.
- interrupts : should contain the AHCI interrupt.
1.c) The FPGA node
The Akebono board stores some board information such as the revision
number in an FPGA which is represented by this node.
Required properties:
- compatible : should be "ibm,akebono-fpga".
- reg : should contain the FPGA registers location and length.
1.d) The AVR node
The Akebono board has an Atmel AVR microprocessor attached to the I2C
bus as a power controller for the board.
Required properties:
- compatible : should be "ibm,akebono-avr".
- reg : should contain the I2C bus address for the AVR.
ppc476gtr High Speed Serial Assist (HSTA) node
==============================================
The 476gtr SoC contains a high speed serial assist module attached
between the plb4 and plb6 system buses to provide high speed data
transfer between memory and system peripherals as well as support for
PCI message signalled interrupts.
Currently only the MSI support is used by Linux using the following
device tree entries:
Require properties:
- compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
- reg : register mapping for the HSTA MSI space
- interrupt-parent : parent controller for mapping interrupts
- interrupts : ordered interrupt mapping for each MSI in the register
space. The first interrupt should be associated with a
register offset of 0x00, the second to 0x10, etc.
......@@ -67,3 +67,20 @@ Example:
gpio-controller;
};
};
* Freescale on-board FPGA connected on I2C bus
Some Freescale boards like BSC9132QDS have on board FPGA connected on
the i2c bus.
Required properties:
- compatible: Should be a board-specific string followed by a string
indicating the type of FPGA. Example:
"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
- reg: Should contain the address of the FPGA
Example:
fpga: fpga@66 {
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
reg = <0x66>;
};
Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
DESCRIPTION
The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
that enables the implementation of coherent, multicore systems.
Required properties:
- compatible: <string list>
fsl,corenet1-cf - CoreNet coherency fabric version 1.
Example chips: T4240, B4860
fsl,corenet2-cf - CoreNet coherency fabric version 2.
Example chips: P5040, P5020, P4080, P3041, P2041
fsl,corenet-cf - Used to represent the common registers
between CCF version 1 and CCF version 2. This compatible
is retained for compatibility reasons, as it was already
used for both CCF version 1 chips and CCF version 2
chips. It should be specified after either
"fsl,corenet1-cf" or "fsl,corenet2-cf".
- reg: <prop-encoded-array>
A standard property. Represents the CCF registers.
- interrupts: <prop-encoded-array>
Interrupt mapping for CCF error interrupt.
- fsl,ccf-num-csdids: <u32>
Specifies the number of Coherency Subdomain ID Port Mapping
Registers that are supported by the CCF.
- fsl,ccf-num-snoopids: <u32>
Specifies the number of Snoop ID Port Mapping Registers that
are supported by CCF.
Example:
corenet-cf@18000 {
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
......@@ -20,3 +20,14 @@ PROPERTIES
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
name with all uppercase letters converted to lowercase, indicates that
the category is supported by the implementation.
- fsl,portid-mapping
Usage: optional
Value type: <u32>
Definition: The Coherency Subdomain ID Port Mapping Registers and
Snoop ID Port Mapping registers, which are part of the CoreNet
Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
these registers should be set if the coresponding CPU should be
snooped. This property defines a bitmask which selects the bit
that should be set if this cpu should be snooped.
......@@ -34,6 +34,15 @@ Optional properties:
for legacy drivers.
- interrupt-parent : <phandle>
Phandle to interrupt controller
- fsl,portid-mapping : <u32>
The Coherency Subdomain ID Port Mapping Registers and
Snoop ID Port Mapping registers, which are part of the
CoreNet Coherency fabric (CCF), provide a CoreNet
Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
functions. Certain bits from these registers should be
set if PAMUs should be snooped. This property defines
a bitmask which selects the bits that should be set if
PAMUs should be snooped.
Child nodes:
......@@ -88,6 +97,7 @@ Example:
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x5000>;
ranges = <0 0x20000 0x5000>;
fsl,portid-mapping = <0xf80000>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <
......
......@@ -142,3 +142,4 @@ wm Wondermedia Technologies, Inc.
xes Extreme Engineering Solutions (X-ES)
xlnx Xilinx
zyxel ZyXEL Communications Corp.
zarlink Zarlink Semiconductor
CPU Families
============
This document tries to summarise some of the different cpu families that exist
and are supported by arch/powerpc.
Book3S (aka sPAPR)
------------------
- Hash MMU
- Mix of 32 & 64 bit
+--------------+ +----------------+
| Old POWER | --------------> | RS64 (threads) |
+--------------+ +----------------+
|
|
v
+--------------+ +----------------+ +------+
| 601 | --------------> | 603 | ---> | e300 |
+--------------+ +----------------+ +------+
| |
| |
v v
+--------------+ +----------------+ +-------+
| 604 | | 750 (G3) | ---> | 750CX |
+--------------+ +----------------+ +-------+
| | |
| | |
v v v
+--------------+ +----------------+ +-------+
| 620 (64 bit) | | 7400 | | 750CL |
+--------------+ +----------------+ +-------+
| | |
| | |
v v v
+--------------+ +----------------+ +-------+
| POWER3/630 | | 7410 | | 750FX |
+--------------+ +----------------+ +-------+
| |
| |
v v
+--------------+ +----------------+
| POWER3+ | | 7450 |
+--------------+ +----------------+
| |
| |
v v
+--------------+ +----------------+
| POWER4 | | 7455 |
+--------------+ +----------------+
| |
| |
v v
+--------------+ +-------+ +----------------+
| POWER4+ | --> | 970 | | 7447 |
+--------------+ +-------+ +----------------+
| | |
| | |
v v v
+--------------+ +-------+ +----------------+
| POWER5 | | 970FX | | 7448 |
+--------------+ +-------+ +----------------+
| | |
| | |
v v v
+--------------+ +-------+ +----------------+
| POWER5+ | | 970MP | | e600 |
+--------------+ +-------+ +----------------+
|
|
v
+--------------+
| POWER5++ |
+--------------+
|
|
v
+--------------+ +-------+
| POWER6 | <-?-> | Cell |
+--------------+ +-------+
|
|
v
+--------------+
| POWER7 |
+--------------+
|
|
v
+--------------+
| POWER7+ |
+--------------+
|
|
v
+--------------+
| POWER8 |
+--------------+
+---------------+
| PA6T (64 bit) |
+---------------+
IBM BookE
---------
- Software loaded TLB.
- All 32 bit
+--------------+
| 401 |
+--------------+
|
|
v
+--------------+
| 403 |
+--------------+
|
|
v
+--------------+
| 405 |
+--------------+
|
|
v
+--------------+
| 440 |
+--------------+
|
|
v
+--------------+ +----------------+
| 450 | --> | BG/P |
+--------------+ +----------------+
|
|
v
+--------------+
| 460 |
+--------------+
|
|
v
+--------------+
| 476 |
+--------------+
Motorola/Freescale 8xx
----------------------
- Software loaded with hardware assist.
- All 32 bit
+-------------+
| MPC8xx Core |
+-------------+
Freescale BookE
---------------
- Software loaded TLB.
- e6500 adds HW loaded indirect TLB entries.
- Mix of 32 & 64 bit
+--------------+
| e200 |
+--------------+
+--------------------------------+
| e500 |
+--------------------------------+
|
|
v
+--------------------------------+
| e500v2 |
+--------------------------------+
|
|
v
+--------------------------------+
| e500mc (Book3e) |
+--------------------------------+
|
|
v
+--------------------------------+
| e5500 (64 bit) |
+--------------------------------+
|
|
v
+--------------------------------+
| e6500 (HW TLB) (Multithreaded) |
+--------------------------------+
IBM A2 core
-----------
- Book3E, software loaded TLB + HW loaded indirect TLB entries.
- 64 bit
+--------------+ +----------------+
| A2 core | --> | WSP |
+--------------+ +----------------+
|
|
v
+--------------+
| BG/Q |
+--------------+
......@@ -453,6 +453,14 @@ config NODES_SHIFT
default "4"
depends on NEED_MULTIPLE_NODES
config USE_PERCPU_NUMA_NODE_ID
def_bool y
depends on NUMA
config HAVE_MEMORYLESS_NODES
def_bool y
depends on NUMA
config ARCH_SELECT_MEMORY_MODEL
def_bool y
depends on PPC64
......
......@@ -113,8 +113,13 @@ else
endif
endif
CFLAGS-$(CONFIG_PPC64) := -mtraceback=no -mcall-aixdesc
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
CFLAGS-$(CONFIG_PPC64) := -mtraceback=no
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,-mcall-aixdesc)
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2)
else
CFLAGS-$(CONFIG_PPC64) += -mcall-aixdesc
endif
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc)
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 $(MULTIPLEWORD)
......@@ -153,7 +158,7 @@ CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
asinstr := $(call as-instr,lis 9$(comma)foo@high,-DHAVE_AS_ATHIGH=1)
KBUILD_CPPFLAGS += -Iarch/$(ARCH) $(asinstr)
KBUILD_AFLAGS += -Iarch/$(ARCH)
KBUILD_AFLAGS += -Iarch/$(ARCH) $(AFLAGS-y)
KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
CPP = $(CC) -E $(KBUILD_CFLAGS)
......@@ -161,6 +166,11 @@ CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
ifeq ($(CONFIG_476FPE_ERR46),y)
KBUILD_LDFLAGS_MODULE += --ppc476-workaround \
-T $(srctree)/arch/powerpc/platforms/44x/ppc476_modules.lds
endif
# No AltiVec or VSX instructions when building kernel
KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
KBUILD_CFLAGS += $(call cc-option,-mno-vsx)
......
......@@ -22,8 +22,14 @@ all: $(obj)/zImage
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -Os -msoft-float -pipe \
-fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
-isystem $(shell $(CROSS32CC) -print-file-name=include) \
-mbig-endian
-isystem $(shell $(CROSS32CC) -print-file-name=include)
ifdef CONFIG_PPC64_BOOT_WRAPPER
BOOTCFLAGS += -m64
endif
ifdef CONFIG_CPU_BIG_ENDIAN
BOOTCFLAGS += -mbig-endian
endif
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
ifdef CONFIG_DEBUG_INFO
......@@ -47,6 +53,7 @@ $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
......@@ -86,6 +93,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-taishan.c cuboot-katmai.c \
cuboot-warp.c cuboot-yosemite.c \
treeboot-iss4xx.c treeboot-currituck.c \
treeboot-akebono.c \
simpleboot.c fixed-head.S virtex.c
src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
......@@ -99,6 +107,11 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
src-wlib := $(sort $(src-wlib-y))
src-plat := $(sort $(src-plat-y))
......@@ -137,7 +150,11 @@ $(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc
$(obj)/empty.c:
@touch $@
$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds: $(obj)/%: $(srctree)/$(src)/%.S
$(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
$(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
$(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
@cp $< $@
clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
......@@ -235,6 +252,7 @@ image-$(CONFIG_YOSEMITE) += cuImage.yosemite
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
treeImage.iss4xx-mpic
image-$(CONFIG_CURRITUCK) += treeImage.currituck
image-$(CONFIG_AKEBONO) += treeImage.akebono
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
......
......@@ -6,6 +6,8 @@
*
* Copyright 2000 Paul Mackerras.
*
* Adapted for 64 bit little endian images by Andrew Tauferner.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
......@@ -55,36 +57,61 @@ unsigned int rpanote[N_RPA_DESCR] = {