Commit da06a8d7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A series of fixes (and in some cases, some cleanups):

  Via Tony Lindgren:
   - A collection of OMAP regression fixes, in particular because
     firmware no longer sets up all pin states before starting the
     kernel.
   - cpufreq fixes for OMAP (Rafael is on vacation and this was
     pre-agreed).
   - A longer series of misc regression fixes and cleanups, warning
     removals, etc for OMAP

  From Arnd Bergmann:
   - A series of warning fixes for various platforms (defconfig builds)

  Misc:
   - A couple of tegra fixes, one for i.MX, some vt8500 fixes, etc."

* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits)
  ARM: pxa: armcore: fix PCI PIO warnings
  ARM: integrator: use __iomem pointers for MMIO, part 2
  ARM: assabet: fix bogus warning in get_assabet_scr (again)
  ARM: shmobile: mark shmobile_init_late as __init
  ARM: integrator_cp: fix build failure
  ARM: OMAP4/AM335x: hwmod: fix disable_module regression in hardreset handling
  ARM: OMAP3: fix workaround for EMU clockdomain
  arm/omap: Replace board_ref_clock with enum values
  ARM: OMAP2+: remove duplicated include from board-omap3stalker.c
  arch/arm/plat-omap/omap-pm-noop.c: Remove unecessary semicolon
  arch/arm/mach-omap2: Remove unecessary semicolon
  arch/arm/mach-omap1/devices.c: Remove unecessary semicolon
  ARM/dts: omap5-evm: pinmux configuration for audio
  ARM/dts: Add pinctrl driver entries for omap5
  ARM/dts: omap4-panda: pinmux configuration for audio
  ARM/dts: omap4-sdp: pinmux configuration for audio
  ARM/dts: omap5-evm: Disable unused McBSP3
  ARM/dts: omap4-sdp: Disable unused McBSP3
  ARM/dts: omap4-panda: Disable unused audio IPs
  ARM: OMAP: board-omap4panda: Pin mux configuration for audio needs
  ...
parents 49999ab2 6bd5dbda
......@@ -7,7 +7,7 @@ as "armctrl" in the SoC documentation, hence naming of this binding.
Required properties:
- compatible : should be "brcm,bcm2835-armctrl-ic.txt"
- compatible : should be "brcm,bcm2835-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
......
......@@ -7,7 +7,7 @@ free running counter values, and generates an interrupt.
Required properties:
- compatible : should be "brcm,bcm2835-system-timer.txt"
- compatible : should be "brcm,bcm2835-system-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupt sinks; one per timer channel.
- clock-frequency : The frequency of the clock that drives the counter, in Hz.
......
......@@ -494,7 +494,6 @@ config ARCH_IOP32X
depends on MMU
select CPU_XSCALE
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
......@@ -508,7 +507,6 @@ config ARCH_IOP33X
depends on MMU
select CPU_XSCALE
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
......@@ -1772,6 +1770,7 @@ source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE
range 11 64 if ARCH_SHMOBILE
default "12" if SOC_AM33XX
default "9" if SA1111
default "11"
help
......
......@@ -25,14 +25,6 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-trats.dtb \
exynos5250-smdk5250.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \
imx53-qsb.dtb \
imx53-smd.dtb
dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-dns325.dtb \
......@@ -76,7 +68,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap4-pandaES.dtb \
omap4-var_som.dtb \
omap4-sdp.dtb \
omap5-evm.dtb
omap5-evm.dtb \
am335x-evm.dtb \
am335x-bone.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
......@@ -104,5 +98,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca15-tc1.dtb \
vexpress-v2p-ca15_a7.dtb \
xenvm-4.2.dtb
dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
wm8505-ref.dtb \
wm8650-mid.dtb
endif
......@@ -59,6 +59,41 @@
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&mcbsp1_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
>;
};
};
&i2c1 {
clock-frequency = <400000>;
......@@ -137,3 +172,15 @@
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&mcbsp2 {
status = "disabled";
};
&mcbsp3 {
status = "disabled";
};
&dmic {
status = "disabled";
};
......@@ -117,6 +117,15 @@
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&dmic_pins
&mcbsp1_pins
&mcbsp2_pins
>;
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
......@@ -141,6 +150,50 @@
0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
>;
};
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
>;
};
dmic_pins: pinmux_dmic_pins {
pinctrl-single,pins = <
0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
>;
};
};
&i2c1 {
......@@ -349,3 +402,7 @@
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&mcbsp3 {
status = "disabled";
};
......@@ -27,6 +27,60 @@
};
&omap5_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&dmic_pins
&mcbsp1_pins
&mcbsp2_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
0x18a 0x6 /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
0x142 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
0x15c 0x108 /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
0x15e 0x108 /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
0x160 0x118 /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
0x162 0x108 /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
>;
};
dmic_pins: pinmux_dmic_pins {
pinctrl-single,pins = <
0x144 0x100 /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
0x146 0x100 /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
0x148 0x100 /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
0x14a 0 /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
0x14c 0x101 /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
0x14e 0x9 /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
0x150 0x101 /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
0x152 0x109 /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
0x154 0x108 /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
0x156 0x8 /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
0x158 0x100 /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
>;
};
};
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
......@@ -82,3 +136,7 @@
0x020700d9>; /* SEARCH */
linux,input-no-autorepeat;
};
&mcbsp3 {
status = "disabled";
};
......@@ -77,6 +77,23 @@
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
omap5_pmx_core: pinmux@4a002840 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a002840 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_pmx_wkup: pinmux@4ae0c840 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4ae0c840 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
......
......@@ -539,7 +539,7 @@
nvidia,invert-interrupt;
};
memory-controller@0x7000f400 {
memory-controller@7000f400 {
emc-table@190000 {
reg = <190000>;
compatible = "nvidia,tegra20-emc-table";
......
......@@ -170,7 +170,7 @@
reg = <0x7000e400 0x400>;
};
memory-controller@0x7000f000 {
memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
......@@ -183,7 +183,7 @@
0x58000000 0x02000000>; /* GART aperture */
};
memory-controller@0x7000f400 {
memory-controller@7000f400 {
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x200>;
#address-cells = <1>;
......
......@@ -284,11 +284,17 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
{
it8152_io.start = IT8152_IO_BASE + 0x12000;
it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
/*
* FIXME: use pci_ioremap_io to remap the IO space here and
* move over to the generic io.h implementation.
* This requires solving the same problem for PXA PCMCIA
* support.
*/
it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
it8152_io.end = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
sys->mem_offset = 0x10000000;
sys->io_offset = IT8152_IO_BASE;
sys->io_offset = (unsigned long)IT8152_IO_BASE;
if (request_resource(&ioport_resource, &it8152_io)) {
printk(KERN_ERR "PCI: unable to allocate IO region\n");
......
......@@ -153,7 +153,9 @@ static int at91_pm_verify_clocks(void)
}
}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS))
return 1;
/* PCK0..PCK3 must be disabled, or configured to use clk32k */
for (i = 0; i < 4; i++) {
u32 css;
......@@ -167,7 +169,6 @@ static int at91_pm_verify_clocks(void)
return 0;
}
}
#endif
return 1;
}
......
......@@ -87,7 +87,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
iotable_init(desc, 1);
}
static struct map_desc at91_io_desc __initdata = {
static struct map_desc at91_io_desc __initdata __maybe_unused = {
.virtual = (unsigned long)AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
......
......@@ -939,7 +939,7 @@ static struct platform_device da850_cpufreq_device = {
unsigned int da850_max_speed = 300000;
int __init da850_register_cpufreq(char *async_clk)
int da850_register_cpufreq(char *async_clk)
{
int i;
......
......@@ -89,8 +89,6 @@
#define IRQ_NETWINDER_VGA _ISA_IRQ(11)
#define IRQ_NETWINDER_SOUND _ISA_IRQ(12)
#undef RTC_IRQ
#define RTC_IRQ IRQ_ISA_RTC_ALARM
#define I8042_KBD_IRQ IRQ_ISA_KEYBOARD
#define I8042_AUX_IRQ (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
#define IRQ_FLOPPYDISK IRQ_ISA_FLOPPY
......
......@@ -3,7 +3,7 @@
*/
void cm_control(u32, u32);
#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL)
#define CM_CTRL_LED (1 << 0)
#define CM_CTRL_nMBDET (1 << 1)
......
......@@ -324,9 +324,9 @@
*/
#define PHYS_PCI_V3_BASE 0x62000000
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
#define PCI_CONFIG_VADDR IOMEM(0xec000000)
#define PCI_V3_VADDR IOMEM(0xed000000)
/* ------------------------------------------------------------------------
* Integrator Interrupt Controllers
......
......@@ -157,7 +157,7 @@ static struct map_desc ap_io_desc[] __initdata = {
static void __init ap_map_io(void)
{
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
vga_base = PCI_MEMORY_VADDR;
vga_base = (unsigned long)PCI_MEMORY_VADDR;
pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
}
......
......@@ -261,6 +261,8 @@ static void __init intcp_init_early(void)
#endif
}
#ifdef CONFIG_OF
static void __init intcp_timer_init_of(void)
{
struct device_node *node;
......@@ -297,8 +299,6 @@ static struct sys_timer cp_of_timer = {
.init = intcp_timer_init_of,
};
#ifdef CONFIG_OF
static const struct of_device_id fpga_irq_of_match[] __initconst = {
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
{ /* Sentinel */ }
......
......@@ -30,7 +30,7 @@
extern int init_atu;
static int __init
iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel < 1 || idsel > 2);
......
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