Commit dff9061b authored by Philippe Gerum's avatar Philippe Gerum
Browse files

arm/mm: l2x0: allow for disabling write-allocate

Re-introduce a config switch (l2x0_write_allocate=) for controlling
the write-allocate policy. Such policy is known to induce very high
latencies: it typically doubles the worst-case figures on imx6q (PL310
cache controller).

By default, the default policy is usually determined by the AWCACHE
attribute settings unless the platform code forced it in the auxiliary
control register. In the common case, write allocation is selected.

The patch applies to L310 and L220 cache controllers exclusively:

- if l2x0_write_allocate= is not set, turn write allocation off.

- if write allocation ends up being enabled, warn about expected high
Signed-off-by: default avatarGilles Chanteperdrix <>
Signed-off-by: Philippe Gerum's avatarPhilippe Gerum <>
parent 3630835f
......@@ -23,6 +23,7 @@
#include <linux/spinlock.h>
#include <linux/log2.h>
#include <linux/io.h>
#include <linux/kconfig.h>
#include <linux/of.h>
#include <linux/of_address.h>
......@@ -49,6 +50,13 @@ struct l2c_init_data {
static int l2x0_wa = -1;
static int __init l2x0_setup_wa(char *str)
l2x0_wa = !!simple_strtol(str, NULL, 0);
return 0;
early_param("l2x0_write_allocate", l2x0_setup_wa);
......@@ -803,6 +811,22 @@ static int __init __l2c_init(const struct l2c_init_data *data,
if (aux_val & aux_mask)
pr_alert("L2C: platform provided aux values permit register corruption.\n");
switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
case L2X0_CACHE_ID_PART_L310:
case L2X0_CACHE_ID_PART_L220:
if (l2x0_wa < 0) {
l2x0_wa = 0;
pr_alert("L2C: I-pipe: l2x0_write_allocate= not specified, defaults to 0 (disabled).\n");
aux_mask &= ~L220_AUX_CTRL_FWA_MASK;
aux_val &= ~L220_AUX_CTRL_FWA_MASK;
aux_val |= (!l2x0_wa) << L220_AUX_CTRL_FWA_SHIFT;
if (l2x0_wa)
pr_alert("L2C: I-pipe: write-allocate enabled, induces high latencies.\n");
old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
aux |= aux_val;
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