Commit f39cf0b7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6:
  xtensa: enable m41t80 driver in s6105_defconfig
  xtensa: add m41t62 rtc to s6105 platform
  xtensa: enable s6gmac in s6105_defconfig
  xtensa: s6105 specific configuration for s6gmac
  s6gmac: xtensa s6000 on-chip ethernet driver
  xtensa: support s6000 gpio irqs and alternate function selection
  xtensa: s6000 dma engine support
  xtensa: allow variant to initialize own irq chips
  xtensa: cache inquiry and unaligned cache handling functions
parents 59ef7a83 aafd1255
......@@ -263,7 +263,54 @@ CONFIG_HAVE_IDE=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_NETDEVICES is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
CONFIG_SMSC_PHY=y
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_NET_ETHERNET is not set
CONFIG_NETDEV_1000=y
CONFIG_S6GMAC=y
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
......@@ -304,8 +351,6 @@ CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
......@@ -387,7 +432,59 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
# CONFIG_RTC_INTF_DEV is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
CONFIG_RTC_DRV_M41T80=y
# CONFIG_RTC_DRV_M41T80_WDT is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
......
......@@ -155,5 +155,100 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*,
#endif
#define XTENSA_CACHEBLK_LOG2 29
#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2)
#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2)
#if XCHAL_HAVE_CACHEATTR
static inline u32 xtensa_get_cacheattr(void)
{
u32 r;
asm volatile(" rsr %0, CACHEATTR" : "=a"(r));
return r;
}
static inline u32 xtensa_get_dtlb1(u32 addr)
{
u32 r = addr & XTENSA_CACHEBLK_MASK;
return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2)))
& 0xF);
}
#else
static inline u32 xtensa_get_dtlb1(u32 addr)
{
u32 r;
asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr));
asm volatile(" dsync");
return r;
}
static inline u32 xtensa_get_cacheattr(void)
{
u32 r = 0;
u32 a = 0;
do {
a -= XTENSA_CACHEBLK_SIZE;
r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF);
} while (a);
return r;
}
#endif
static inline int xtensa_need_flush_dma_source(u32 addr)
{
return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4;
}
static inline int xtensa_need_invalidate_dma_destination(u32 addr)
{
return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2;
}
static inline void flush_dcache_unaligned(u32 addr, u32 size)
{
u32 cnt;
if (size) {
cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
while (cnt--) {
asm volatile(" dhwb %0, 0" : : "a"(addr));
addr += XCHAL_DCACHE_LINESIZE;
}
asm volatile(" dsync");
}
}
static inline void invalidate_dcache_unaligned(u32 addr, u32 size)
{
int cnt;
if (size) {
asm volatile(" dhwbi %0, 0 ;" : : "a"(addr));
cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
- XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
while (cnt-- > 0) {
asm volatile(" dhi %0, %1" : : "a"(addr),
"n"(XCHAL_DCACHE_LINESIZE));
addr += XCHAL_DCACHE_LINESIZE;
}
asm volatile(" dhwbi %0, %1" : : "a"(addr),
"n"(XCHAL_DCACHE_LINESIZE));
asm volatile(" dsync");
}
}
static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
{
u32 cnt;
if (size) {
cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
while (cnt--) {
asm volatile(" dhwbi %0, 0" : : "a"(addr));
addr += XCHAL_DCACHE_LINESIZE;
}
asm volatile(" dsync");
}
}
#endif /* __KERNEL__ */
#endif /* _XTENSA_CACHEFLUSH_H */
......@@ -38,14 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
/*
* Not implemented, yet.
*/
static inline int gpio_to_irq(unsigned int gpio)
{
return -ENOSYS;
return __gpio_to_irq(gpio);
}
/*
* Not implemented, yet.
*/
static inline int irq_to_gpio(unsigned int irq)
{
return -EINVAL;
......
......@@ -11,6 +11,7 @@
#ifndef _XTENSA_IRQ_H
#define _XTENSA_IRQ_H
#include <linux/init.h>
#include <platform/hardware.h>
#include <variant/core.h>
......@@ -21,11 +22,20 @@ static inline void variant_irq_enable(unsigned int irq) { }
static inline void variant_irq_disable(unsigned int irq) { }
#endif
#ifndef VARIANT_NR_IRQS
# define VARIANT_NR_IRQS 0
#endif
#ifndef PLATFORM_NR_IRQS
# define PLATFORM_NR_IRQS 0
#endif
#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS)
#if VARIANT_NR_IRQS == 0
static inline void variant_init_irq(void) { }
#else
void variant_init_irq(void) __init;
#endif
static __inline__ int irq_canonicalize(int irq)
{
......
......@@ -197,4 +197,6 @@ void __init init_IRQ(void)
}
cached_irq_mask = 0;
variant_init_irq();
}
......@@ -5,14 +5,27 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <variant/hardware.h>
#include <variant/dmac.h>
#include <platform/gpio.h>
#define GPIO3_INTNUM 3
#define UART_INTNUM 4
#define GMAC_INTNUM 5
static const signed char gpio3_irq_mappings[] = {
S6_INTC_GPIO(3),
-1
};
static const signed char uart_irq_mappings[] = {
S6_INTC_UART(0),
......@@ -20,8 +33,18 @@ static const signed char uart_irq_mappings[] = {
-1,
};
static const signed char gmac_irq_mappings[] = {
S6_INTC_GMAC_STAT,
S6_INTC_GMAC_ERR,
S6_INTC_DMA_HOSTTERMCNT(0),
S6_INTC_DMA_HOSTTERMCNT(1),
-1
};
const signed char *platform_irq_mappings[NR_IRQS] = {
[GPIO3_INTNUM] = gpio3_irq_mappings,
[UART_INTNUM] = uart_irq_mappings,
[GMAC_INTNUM] = gmac_irq_mappings,
};
static struct plat_serial8250_port serial_platform_data[] = {
......@@ -46,6 +69,66 @@ static struct plat_serial8250_port serial_platform_data[] = {
{ },
};
static struct resource s6_gmac_resource[] = {
{
.name = "mem",
.start = (resource_size_t)S6_REG_GMAC,
.end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "dma",
.start = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX),
.end = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1,
.flags = IORESOURCE_DMA,
},
{
.name = "dma",
.start = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX),
.end = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1,
.flags = IORESOURCE_DMA,
},
{
.name = "io",
.start = (resource_size_t)S6_MEM_GMAC,
.end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1,
.flags = IORESOURCE_IO,
},
{
.name = "irq",
.start = (resource_size_t)GMAC_INTNUM,
.flags = IORESOURCE_IRQ,
},
{
.name = "irq",
.start = (resource_size_t)PHY_POLL,
.flags = IORESOURCE_IRQ,
},
};
static int __init prepare_phy_irq(int pin)
{
int irq;
if (gpio_request(pin, "s6gmac_phy") < 0)
goto fail;
if (gpio_direction_input(pin) < 0)
goto free;
irq = gpio_to_irq(pin);
if (irq < 0)
goto free;
if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
goto free;
return irq;
free:
gpio_free(pin);
fail:
return PHY_POLL;
}
static struct platform_device platform_devices[] = {
{
.name = "serial8250",
......@@ -54,12 +137,23 @@ static struct platform_device platform_devices[] = {
.platform_data = serial_platform_data,
},
},
{
.name = "s6gmac",
.id = 0,
.resource = s6_gmac_resource,
.num_resources = ARRAY_SIZE(s6_gmac_resource),
},
{
I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62),
},
};
static int __init device_init(void)
{
int i;
s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ);
for (i = 0; i < ARRAY_SIZE(platform_devices); i++)
platform_device_register(&platform_devices[i]);
return 0;
......
......@@ -35,12 +35,21 @@ void __init platform_setup(char **cmdline)
{
unsigned long reg;
reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC |
S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII);
reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC |
S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII;
writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL);
reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE);
reg &= ~(1 << S6_GREG1_BLOCK_SB);
reg &= ~(1 << S6_GREG1_BLOCK_GMAC);
writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE);
reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA);
reg |= 1 << S6_GREG1_BLOCK_SB;
reg |= 1 << S6_GREG1_BLOCK_GMAC;
writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA);
printk(KERN_NOTICE "S6105 on Stretch S6000 - "
......@@ -49,7 +58,7 @@ void __init platform_setup(char **cmdline)
void __init platform_init(bp_tag_t *first)
{
s6_gpio_init();
s6_gpio_init(0);
gpio_request(GPIO_LED1_NGREEN, "led1_green");
gpio_request(GPIO_LED1_RED, "led1_red");
gpio_direction_output(GPIO_LED1_NGREEN, 1);
......
# s6000 Makefile
obj-y += irq.o gpio.o
obj-y += irq.o gpio.o dmac.o
obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o
/*
* Authors: Oskar Schirmer <os@emlix.com>
* Daniel Gloeckner <dg@emlix.com>
* (c) 2008 emlix GmbH http://www.emlix.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <asm/cacheflush.h>
#include <variant/dmac.h>
/* DMA engine lookup */
struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
/* DMA control, per engine */
void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
{
if (xtensa_need_flush_dma_source(src)) {
u32 base = src;
u32 span = size;
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
if (chunk && (size > chunk)) {
s32 skip =
readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
u32 gaps = (size+chunk-1)/chunk - 1;
if (skip >= 0) {
span += gaps * skip;
} else if (-skip > chunk) {
s32 decr = gaps * (chunk + skip);
base += decr;
span = chunk - decr;
} else {
span = max(span + gaps * skip,
(chunk + skip) * gaps - skip);
}
}
flush_dcache_unaligned(base, span);
}
if (xtensa_need_invalidate_dma_destination(dst)) {
u32 base = dst;
u32 span = size;
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
if (chunk && (size > chunk)) {
s32 skip =
readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
u32 gaps = (size+chunk-1)/chunk - 1;
if (skip >= 0) {
span += gaps * skip;
} else if (-skip > chunk) {
s32 decr = gaps * (chunk + skip);
base += decr;
span = chunk - decr;
} else {
span = max(span + gaps * skip,
(chunk + skip) * gaps - skip);
}
}
invalidate_dcache_unaligned(base, span);
}
s6dmac_put_fifo(dmac, chan, src, dst, size);
}
void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
{
unsigned long flags;
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
spin_lock_irqsave(spinl, flags);
_s6dmac_disable_error_irqs(dmac, mask);
spin_unlock_irqrestore(spinl, flags);
}
u32 s6dmac_int_sources(u32 dmac, u32 channel)
{
u32 mask, ret, tmp;
mask = 1 << channel;
tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
ret = tmp >> channel;
tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
ret |= (tmp >> channel) << 1;
tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
ret |= (tmp >> channel) << 2;
tmp = readl(dmac + S6_DMA_INTRAW0);
tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
writel(tmp, dmac + S6_DMA_INTCLEAR0);
if (tmp & (mask << S6_DMA_INT0_UNDER))
ret |= 1 << 3;
if (tmp & (mask << S6_DMA_INT0_OVER))
ret |= 1 << 4;
tmp = readl(dmac + S6_DMA_MASTERERRINFO);
mask <<= S6_DMA_INT1_CHANNEL;
if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << S6_DMA_INT1_MASTER;
if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << (S6_DMA_INT1_MASTER + 1);
if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << (S6_DMA_INT1_MASTER + 2);
tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
writel(tmp, dmac + S6_DMA_INTCLEAR1);
ret |= ((tmp >> channel) & 1) << 5;
ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
return ret;
}
void s6dmac_release_chan(u32 dmac, int chan)
{
if (chan >= 0)
s6dmac_disable_chan(dmac, chan);
}
/* global init */
static inline void __init dmac_init(u32 dmac, u8 chan_nb)
{
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
dmac + S6_DMA_INTCLEAR1);
}
static inline void __init dmac_master(u32 dmac,
u32 m0start, u32 m0end, u32 m1start, u32 m1end)
{
writel(m0start, dmac + S6_DMA_MASTER0START);
writel(m0end - 1, dmac + S6_DMA_MASTER0END);
writel(m1start, dmac + S6_DMA_MASTER1START);
writel(m1end - 1, dmac + S6_DMA_MASTER1END);
}
static void __init s6_dmac_init(void)
{
dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);