1. 30 Aug, 2013 2 commits
  2. 13 Aug, 2013 13 commits
    • Chris Metcalf's avatar
      tile: provide traceability for hypervisor calls · 9ae09838
      Chris Metcalf authored
      
      
      This change adds infrastructure (CONFIG_TILE_HVGLUE_TRACE) that
      provides C code wrappers for the calls the kernel makes to the Tilera
      hypervisor.  This allows standard kernel infrastructure like FTRACE to
      be able to instrument hypervisor calls.
      
      To allow direct calls to the true API, we export their names with a
      leading underscore as well.  This is important for the few contexts
      where we need to make hypervisor calls without touching the stack.
      
      As part of this change, we also switch from creating the symbols
      with linker magic to creating them with assembler magic.  This lets
      us provide a symbol type and generally make them appear more as symbols
      and less as just random values in the Elf namespace.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      9ae09838
    • Chris Metcalf's avatar
      tile: avoid struct vm_struct leak · fad052dc
      Chris Metcalf authored
      
      
      If ioreamp_prot() fails in ioremap_page_range() due to kernel memory
      exhaustion, we previously would leak a struct vm_struct.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      fad052dc
    • Chris Metcalf's avatar
      tile: implement gettimeofday() via vDSO · 4a556f4f
      Chris Metcalf authored
      
      
      This change creates the framework for vDSO calls, makes the existing
      rt_sigreturn() mechanism use it, and adds a fast gettimeofday().
      Now that we need to expose the vDSO address to userspace, we add
      AT_SYSINFO_EHDR to the set of aux entries provided to userspace.
      (You can disable any extra vDSO support by booting with vdso=0,
      but the rt_sigreturn vDSO page will still be provided.)
      
      Note that glibc has supported the tile vDSO since release 2.17.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      4a556f4f
    • Chris Metcalf's avatar
      tile: support simulator notification for ET_DYN objects · 0c1d1917
      Chris Metcalf authored
      
      
      The tile code notifies the simulator of new ET_EXEC objects starting
      to execute so that tracing code can properly annotate the objects.
      However, we didn't support ET_DYN executables like ld.so, so we
      didn't properly load symbols, etc.  This change enables that support;
      we use a variant of the SIM_CONTROL_DLOPEN simulator notification
      that newer simulators will recognize and use to set the base address
      for the next SIM_CONTROL_OS_EXEC notification.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      0c1d1917
    • Chris Metcalf's avatar
      tile: improve illegal translation interrupt handling · 70d2b595
      Chris Metcalf authored
      
      
      First, don't re-enable interrupts blindly in the Linux trap handler.
      We already handle page faults this way; synchronous interrupts like
      ILL_TRANS will fire even when interrupts are disabled, and we don't
      want to re-enable interrupts in that case.
      
      For ILL_TRANS, we now pass the ILL_VA_PC reason into the trap handler
      so we can report it properly; this is the address that caused the
      illegal translation trap.  We print the address as part of the
      pr_alert() message now if it's coming from the kernel.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      70d2b595
    • Chris Metcalf's avatar
      tile: make register dumps more readable · dadf78bf
      Chris Metcalf authored
      
      
      It's much easier to read register dumps if you read vertically
      rather than horizontally, since the register numbers line up
      and lead the eye down more than to the right.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      dadf78bf
    • Chris Metcalf's avatar
      tile: improve big-endian support · ba02f0eb
      Chris Metcalf authored
      
      
      First, fix a bug in asm/unaligned.h; we need to just use the asm-generic
      unaligned.h so we properly choose endian-correct flavors.
      
      Second, keep the hv/hypervisor.h ABI fully "native" in the sense that
      we don't have __BIG_ENDIAN__ ifdefs there.  Instead, we use macros in
      the head_NN.S assembly code to properly extract two 32-bit structure
      members from a 64-bit register holding the structure.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      ba02f0eb
    • Chris Metcalf's avatar
      tile: support CONFIG_PREEMPT · bc1a298f
      Chris Metcalf authored
      
      
      This change adds support for CONFIG_PREEMPT (full kernel preemption).
      In addition to the core support, this change includes a number
      of places where we fix up uses of smp_processor_id() and per-cpu
      variables.  I also eliminate the PAGE_HOME_HERE and PAGE_HOME_UNKNOWN
      values for page homing, as it turns out they weren't being used.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      bc1a298f
    • Chris Metcalf's avatar
      tile: remove calls to arch_flush_lazy_mmu_mode() · 1182b69c
      Chris Metcalf authored
      
      
      Since it's a no-op on tile anyway, there's no reason to be calling
      it in tile-specific code.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      1182b69c
    • Chris Metcalf's avatar
      tile: fix some issues in hugepage support · a0bd12d7
      Chris Metcalf authored
      
      
      First, in huge_pte_offset(), we were erroneously checking
      pgd_present(), which is always true, rather than pud_present(),
      which is the thing that tells us if there is a top-level (L0) PTE.
      Fixing this means we properly look up huge page entries only when
      the Present bit is actually set in the PTE.
      
      Second, use the standard pte_alloc_map() instead of the hand-rolled
      pte_alloc_hugetlb() routine that basically was written to avoid
      worrying about CONFIG_HIGHPTE.  However, we no longer plan to support
      HIGHPTE, so a separate routine was just unnecessary code duplication.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      a0bd12d7
    • Chris Metcalf's avatar
      tile: add some tile drivers to MAINTAINERS · 6b940606
      Chris Metcalf authored
      
      
      Also, alphabetize the existing entries for tile.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      6b940606
    • Chris Metcalf's avatar
      tile: avoid recursive backtrace faults · 3ef23111
      Chris Metcalf authored
      
      
      This change adds support for avoiding recursive backtracer crashes;
      we haven't seen this in practice other than when things are seriously
      corrupt, but it may help avoid losing the root cause of a crash.
      
      Also, don't abort kernel backtracers for invalid userspace PC's.
      If we do, we lose the ability to backtrace through a userspace
      call to a bad address above PAGE_OFFSET, even though that it can
      be perfectly reasonable to continue the backtrace in such a case.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      3ef23111
    • Chris Metcalf's avatar
      tile: fast-path unaligned memory access for tilegx · 2f9ac29e
      Chris Metcalf authored
      
      
      This change enables unaligned userspace memory access via a kernel
      fast path on tilegx.  The kernel tracks user PC/instruction pairs
      per-thread using a direct-mapped cache in userspace.  The cache
      maps those PC/instruction pairs to JIT'ed instruction sequences that
      load or store using byte-wide load store intructions and then
      synthesize 2-, 4- or 8-byte load or store results.  Once an
      instruction has been seen to generate an unaligned access once,
      subsequent hits on that instruction typically require overhead
      of only around 50 cycles if cache and TLB is hot.
      
      We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to
      enable or disable unaligned fixups on a per-process basis.
      
      To do this we pull some of the tilepro unaligned support out of the
      single_step.c file; tilepro uses instruction disassembly for both
      single-step and unaligned access support.  Since tilegx actually has
      hardware singlestep support, though, it's cleaner to keep the tilegx
      unaligned access code in a separate file.  While we're at it,
      properly rename the tilepro-specific types, etc., to have tilepro
      suffixes instead of generic tile suffixes.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      2f9ac29e
  3. 12 Aug, 2013 5 commits
    • Chris Metcalf's avatar
      tile: remove unnecessary backslashes in asm-offsets.c · f10da547
      Chris Metcalf authored
      
      
      Pointed out by checkpatch.  A few of the DEFINE() lines were
      properly written without backslash continuation; fix the rest.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      f10da547
    • Chris Metcalf's avatar
      tile: fix tilegx vmalloc_sync_all BUG_ON · e5f7bd43
      Chris Metcalf authored
      
      
      As specified, the test wasn't correct, and in any case it should
      be a BUILD_BUG_ON.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      e5f7bd43
    • Chris Metcalf's avatar
      b63ea712
    • Chris Metcalf's avatar
      tile: support "memmap" boot parameter · 77f8c740
      Chris Metcalf authored
      
      
      This change adds support for the "memmap" boot parameter similar
      to what x86 provides.  The tile version supports "memmap=1G$5G",
      for example, as a way to reserve a 1 GB range starting at PA 5GB.
      The memory is reserved via bootmem during startup, and we create a
      suitable "struct resource" marked as "Reserved" so you can see the
      range reported by /proc/iomem.  Up to 64 such regions can currently
      be reserved on the boot command line.
      
      We do not support the x86 options "memmap=nn@ss" (force some memory
      to be available at the given address) since it's pointless to try to
      have Linux use memory the Tilera hypervisor hasn't given it.  We do
      not support "memmap=nn#ss" to add an ACPI range for later processing,
      since we don't support ACPI.  We do not support "memmap=exactmap"
      since we don't support reading the e820 information from the BIOS
      like x86 does.  I did add support for "memmap=nn" (and the synonym
      "mem=nn") which cap the highest PA value at "nn"; these are both
      just a synonym for the existing tile boot option "maxmem".
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      77f8c740
    • Chris Metcalf's avatar
      tile: various console improvements · bda0f5ba
      Chris Metcalf authored
      
      
      This change improves and cleans up the tile console.
      
      - We enable HVC_IRQ support on tilegx, with the addition of a new
        Tilera hypervisor API for tilegx to allow a console IPI.  If IPI
        support is not available we fall back to the previous polling mode.
      
      - We simplify the earlyprintk code to use CON_BOOT and eliminate some
        of the other supporting earlyprintk code.
      
      - A new tile_console_write() primitive is used to send output to
        the console and is factored out of the hvc_tile driver.
        This lets us support a "sim_console" boot argument to allow using
        simulator hooks to send output to the "console" as a slightly
        faster alternative to emulating the hardware more directly.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      bda0f5ba
  4. 06 Aug, 2013 15 commits
  5. 05 Aug, 2013 5 commits