1. 25 Jul, 2008 3 commits
    • Arthur Jones's avatar
      edac: i5100 fix enable ecc hardware · 43920a59
      Arthur Jones authored
      
      
      It is possible that the BIOS did not enable ECC at boot time.  We check
      for that case and fail to load if it is true.
      
      Signed-off-by: default avatarArthur Jones <ajones@riverbed.com>
      Signed-off-by: default avatarDoug Thompson <dougthompson@xmission.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      43920a59
    • Arthur Jones's avatar
      edac: i5100 fix missing bits · f7952ffc
      Arthur Jones authored
      
      
      The error mask we use to trigger ECC notifications is missing many bits of
      interest.  We add these bits here so that all possible ECC errors can be
      reported.
      
      Signed-off-by: default avatarArthur Jones <ajones@riverbed.com>
      Signed-off-by: default avatarDoug Thompson <dougthompson@xmission.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      f7952ffc
    • Arthur Jones's avatar
      edac: i5100 new intel chipset driver · 8f421c59
      Arthur Jones authored
      
      
      Preliminary support for the Intel 5100 MCH.  CE and UE errors are reported
      along with the current DIMM label information and other memory parameters.
      
      Reasons why this is preliminary:
      
      1) This chip has 2 independent memory controllers which, for best
         perforance, use interleaved accesses to the DDR2 memory.  This
         architecture does not map very well to the current edac data structures
         which depend on symmetric channel access to the interleaved data.
         Without core changes, the best I could do for now is to map both memory
         controllers to different csrows (first all ranks of controller 0, then
         all ranks of controller 1).  Someone much more familiar with the edac
         core than I will probably need to come up with a more general data
         structure to handle the interleaving and de-interleaving of the two
         memory controllers.
      
      2) I have not yet tackled the de-interleaving of the rank/controller
         address space into the physical address space of the CPU.  There is
         nothing fundamentally missing, it is just ending up to be a lot of
         code, and I'd rather keep it separate for now, esp since it doesn't
         work yet...
      
      3) The code depends on a particular i5100 chip select to DIMM mainboard
         chip select mapping.  This mapping seems obvious to me in order to
         support dual and single ranked memory, but it is not unique and DIMM
         labels could be wrong on other mainboards.  There is no way to query
         this mapping that I know of.
      
      4) The code requires that the i5100 is in 32GB mode.  Only 4 ranks per
         controller, 2 ranks per DIMM are supported.  I do not have hardware
         (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks
         per controller) mode.
      
      5) The serial presence detect code should be broken out into a "real"
         i2c driver so that decode-dimms.pl can work.
      
      Signed-off-by: default avatarArthur Jones <ajones@riverbed.com>
      Signed-off-by: default avatarDoug Thompson <dougthompson@xmission.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      8f421c59