1. 16 Apr, 2013 1 commit
  2. 04 Mar, 2013 4 commits
  3. 25 Feb, 2013 1 commit
  4. 11 Feb, 2013 8 commits
  5. 23 Jan, 2013 8 commits
    • Marc Zyngier's avatar
      KVM: ARM: Power State Coordination Interface implementation · aa024c2f
      Marc Zyngier authored
      
      
      Implement the PSCI specification (ARM DEN 0022A) to control
      virtual CPUs being "powered" on or off.
      
      PSCI/KVM is detected using the KVM_CAP_ARM_PSCI capability.
      
      A virtual CPU can now be initialized in a "powered off" state,
      using the KVM_ARM_VCPU_POWER_OFF feature flag.
      
      The guest can use either SMC or HVC to execute a PSCI function.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      aa024c2f
    • Christoffer Dall's avatar
      KVM: ARM: Handle I/O aborts · 45e96ea6
      Christoffer Dall authored
      
      
      When the guest accesses I/O memory this will create data abort
      exceptions and they are handled by decoding the HSR information
      (physical address, read/write, length, register) and forwarding reads
      and writes to QEMU which performs the device emulation.
      
      Certain classes of load/store operations do not support the syndrome
      information provided in the HSR.  We don't support decoding these (patches
      are available elsewhere), so we report an error to user space in this case.
      
      This requires changing the general flow somewhat since new calls to run
      the VCPU must check if there's a pending MMIO load and perform the write
      after userspace has made the data available.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      45e96ea6
    • Christoffer Dall's avatar
      KVM: ARM: Emulation framework and CP15 emulation · 5b3e5e5b
      Christoffer Dall authored
      
      
      Adds a new important function in the main KVM/ARM code called
      handle_exit() which is called from kvm_arch_vcpu_ioctl_run() on returns
      from guest execution. This function examines the Hyp-Syndrome-Register
      (HSR), which contains information telling KVM what caused the exit from
      the guest.
      
      Some of the reasons for an exit are CP15 accesses, which are
      not allowed from the guest and this commit handles these exits by
      emulating the intended operation in software and skipping the guest
      instruction.
      
      Minor notes about the coproc register reset:
      1) We reserve a value of 0 as an invalid cp15 offset, to catch bugs in our
         table, at cost of 4 bytes per vcpu.
      
      2) Added comments on the table indicating how we handle each register, for
         simplicity of understanding.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      5b3e5e5b
    • Christoffer Dall's avatar
      KVM: ARM: World-switch implementation · f7ed45be
      Christoffer Dall authored
      
      
      Provides complete world-switch implementation to switch to other guests
      running in non-secure modes. Includes Hyp exception handlers that
      capture necessary exception information and stores the information on
      the VCPU and KVM structures.
      
      The following Hyp-ABI is also documented in the code:
      
      Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
         Switching to Hyp mode is done through a simple HVC #0 instruction. The
         exception vector code will check that the HVC comes from VMID==0 and if
         so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
         - r0 contains a pointer to a HYP function
         - r1, r2, and r3 contain arguments to the above function.
         - The HYP function will be called with its arguments in r0, r1 and r2.
         On HYP function return, we return directly to SVC.
      
      A call to a function executing in Hyp mode is performed like the following:
      
              <svc code>
              ldr     r0, =BSYM(my_hyp_fn)
              ldr     r1, =my_param
              hvc #0  ; Call my_hyp_fn(my_param) from HYP mode
              <svc code>
      
      Otherwise, the world-switch is pretty straight-forward. All state that
      can be modified by the guest is first backed up on the Hyp stack and the
      VCPU values is loaded onto the hardware. State, which is not loaded, but
      theoretically modifiable by the guest is protected through the
      virtualiation features to generate a trap and cause software emulation.
      Upon guest returns, all state is restored from hardware onto the VCPU
      struct and the original state is restored from the Hyp-stack onto the
      hardware.
      
      SMP support using the VMPIDR calculated on the basis of the host MPIDR
      and overriding the low bits with KVM vcpu_id contributed by Marc Zyngier.
      
      Reuse of VMIDs has been implemented by Antonios Motakis and adapated from
      a separate patch into the appropriate patches introducing the
      functionality. Note that the VMIDs are stored per VM as required by the ARM
      architecture reference manual.
      
      To support VFP/NEON we trap those instructions using the HPCTR. When
      we trap, we switch the FPU.  After a guest exit, the VFP state is
      returned to the host.  When disabling access to floating point
      instructions, we also mask FPEXC_EN in order to avoid the guest
      receiving Undefined instruction exceptions before we have a chance to
      switch back the floating point state.  We are reusing vfp_hard_struct,
      so we depend on VFPv3 being enabled in the host kernel, if not, we still
      trap cp10 and cp11 in order to inject an undefined instruction exception
      whenever the guest tries to use VFP/NEON. VFP/NEON developed by
      Antionios Motakis and Rusty Russell.
      
      Aborts that are permission faults, and not stage-1 page table walk, do
      not report the faulting address in the HPFAR.  We have to resolve the
      IPA, and store it just like the HPFAR register on the VCPU struct. If
      the IPA cannot be resolved, it means another CPU is playing with the
      page tables, and we simply restart the guest.  This quirk was fixed by
      Marc Zyngier.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarAntonios Motakis <a.motakis@virtualopensystems.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      f7ed45be
    • Christoffer Dall's avatar
      KVM: ARM: Inject IRQs and FIQs from userspace · 86ce8535
      Christoffer Dall authored
      
      
      All interrupt injection is now based on the VM ioctl KVM_IRQ_LINE.  This
      works semantically well for the GIC as we in fact raise/lower a line on
      a machine component (the gic).  The IOCTL uses the follwing struct.
      
      struct kvm_irq_level {
      	union {
      		__u32 irq;     /* GSI */
      		__s32 status;  /* not used for KVM_IRQ_LEVEL */
      	};
      	__u32 level;           /* 0 or 1 */
      };
      
      ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
      (GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
      specific cpus.  The irq field is interpreted like this:
      
        bits:  | 31 ... 24 | 23  ... 16 | 15    ...    0 |
        field: | irq_type  | vcpu_index |   irq_number   |
      
      The irq_type field has the following values:
      - irq_type[0]: out-of-kernel GIC: irq_number 0 is IRQ, irq_number 1 is FIQ
      - irq_type[1]: in-kernel GIC: SPI, irq_number between 32 and 1019 (incl.)
                     (the vcpu_index field is ignored)
      - irq_type[2]: in-kernel GIC: PPI, irq_number between 16 and 31 (incl.)
      
      The irq_number thus corresponds to the irq ID in as in the GICv2 specs.
      
      This is documented in Documentation/kvm/api.txt.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      86ce8535
    • Christoffer Dall's avatar
      KVM: ARM: Memory virtualization setup · d5d8184d
      Christoffer Dall authored
      
      
      This commit introduces the framework for guest memory management
      through the use of 2nd stage translation. Each VM has a pointer
      to a level-1 table (the pgd field in struct kvm_arch) which is
      used for the 2nd stage translations. Entries are added when handling
      guest faults (later patch) and the table itself can be allocated and
      freed through the following functions implemented in
      arch/arm/kvm/arm_mmu.c:
       - kvm_alloc_stage2_pgd(struct kvm *kvm);
       - kvm_free_stage2_pgd(struct kvm *kvm);
      
      Each entry in TLBs and caches are tagged with a VMID identifier in
      addition to ASIDs. The VMIDs are assigned consecutively to VMs in the
      order that VMs are executed, and caches and tlbs are invalidated when
      the VMID space has been used to allow for more than 255 simultaenously
      running guests.
      
      The 2nd stage pgd is allocated in kvm_arch_init_vm(). The table is
      freed in kvm_arch_destroy_vm(). Both functions are called from the main
      KVM code.
      
      We pre-allocate page table memory to be able to synchronize using a
      spinlock and be called under rcu_read_lock from the MMU notifiers.  We
      steal the mmu_memory_cache implementation from x86 and adapt for our
      specific usage.
      
      We support MMU notifiers (thanks to Marc Zyngier) through
      kvm_unmap_hva and kvm_set_spte_hva.
      
      Finally, define kvm_phys_addr_ioremap() to map a device at a guest IPA,
      which is used by VGIC support to map the virtual CPU interface registers
      to the guest. This support is added by Marc Zyngier.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      d5d8184d
    • Christoffer Dall's avatar
      KVM: ARM: Hypervisor initialization · 342cd0ab
      Christoffer Dall authored
      
      
      Sets up KVM code to handle all exceptions taken to Hyp mode.
      
      When the kernel is booted in Hyp mode, calling an hvc instruction with r0
      pointing to the new vectors, the HVBAR is changed to the the vector pointers.
      This allows subsystems (like KVM here) to execute code in Hyp-mode with the
      MMU disabled.
      
      We initialize other Hyp-mode registers and enables the MMU for Hyp-mode from
      the id-mapped hyp initialization code. Afterwards, the HVBAR is changed to
      point to KVM Hyp vectors used to catch guest faults and to switch to Hyp mode
      to perform a world-switch into a KVM guest.
      
      Also provides memory mapping code to map required code pages, data structures,
      and I/O regions  accessed in Hyp mode at the same virtual address as the host
      kernel virtual addresses, but which conforms to the architectural requirements
      for translations in Hyp mode. This interface is added in arch/arm/kvm/arm_mmu.c
      and comprises:
       - create_hyp_mappings(from, to);
       - create_hyp_io_mappings(from, to, phys_addr);
       - free_hyp_pmds();
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      342cd0ab
    • Christoffer Dall's avatar
      KVM: ARM: Initial skeleton to compile KVM support · 749cf76c
      Christoffer Dall authored
      
      
      Targets KVM support for Cortex A-15 processors.
      
      Contains all the framework components, make files, header files, some
      tracing functionality, and basic user space API.
      
      Only supported core is Cortex-A15 for now.
      
      Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.
      
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <c.dall@virtualopensystems.com>
      749cf76c