1. 17 Apr, 2013 1 commit
  2. 22 Mar, 2013 1 commit
  3. 05 Oct, 2012 3 commits
    • Paul Mackerras's avatar
      KVM: PPC: Book3S: Get/set guest FP regs using the GET/SET_ONE_REG interface · a8bd19ef
      Paul Mackerras authored
      
      
      This enables userspace to get and set all the guest floating-point
      state using the KVM_[GS]ET_ONE_REG ioctls.  The floating-point state
      includes all of the traditional floating-point registers and the
      FPSCR (floating point status/control register), all the VMX/Altivec
      vector registers and the VSCR (vector status/control register), and
      on POWER7, the vector-scalar registers (note that each FP register
      is the high-order half of the corresponding VSR).
      
      Most of these are implemented in common Book 3S code, except for VSX
      on POWER7.  Because HV and PR differ in how they store the FP and VSX
      registers on POWER7, the code for these cases is not common.  On POWER7,
      the FP registers are the upper halves of the VSX registers vsr0 - vsr31.
      PR KVM stores vsr0 - vsr31 in two halves, with the upper halves in the
      arch.fpr[] array and the lower halves in the arch.vsr[] array, whereas
      HV KVM on POWER7 stores the whole VSX register in arch.vsr[].
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      [agraf: fix whitespace, vsx compilation]
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      a8bd19ef
    • Paul Mackerras's avatar
      KVM: PPC: Book3S: Get/set guest SPRs using the GET/SET_ONE_REG interface · a136a8bd
      Paul Mackerras authored
      
      
      This enables userspace to get and set various SPRs (special-purpose
      registers) using the KVM_[GS]ET_ONE_REG ioctls.  With this, userspace
      can get and set all the SPRs that are part of the guest state, either
      through the KVM_[GS]ET_REGS ioctls, the KVM_[GS]ET_SREGS ioctls, or
      the KVM_[GS]ET_ONE_REG ioctls.
      
      The SPRs that are added here are:
      
      - DABR:  Data address breakpoint register
      - DSCR:  Data stream control register
      - PURR:  Processor utilization of resources register
      - SPURR: Scaled PURR
      - DAR:   Data address register
      - DSISR: Data storage interrupt status register
      - AMR:   Authority mask register
      - UAMOR: User authority mask override register
      - MMCR0, MMCR1, MMCRA: Performance monitor unit control registers
      - PMC1..PMC8: Performance monitor unit counter registers
      
      In order to reduce code duplication between PR and HV KVM code, this
      moves the kvm_vcpu_ioctl_[gs]et_one_reg functions into book3s.c and
      centralizes the copying between user and kernel space there.  The
      registers that are handled differently between PR and HV, and those
      that exist only in one flavor, are handled in kvmppc_[gs]et_one_reg()
      functions that are specific to each flavor.
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      [agraf: minimal style fixes]
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      a136a8bd
    • Bharat Bhushan's avatar
      KVM: PPC: booke: Add watchdog emulation · f61c94bb
      Bharat Bhushan authored
      
      
      This patch adds the watchdog emulation in KVM. The watchdog
      emulation is enabled by KVM_ENABLE_CAP(KVM_CAP_PPC_BOOKE_WATCHDOG) ioctl.
      The kernel timer are used for watchdog emulation and emulates
      h/w watchdog state machine. On watchdog timer expiry, it exit to QEMU
      if TCR.WRC is non ZERO. QEMU can reset/shutdown etc depending upon how
      it is configured.
      
      Signed-off-by: default avatarLiu Yu <yu.liu@freescale.com>
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      [bharat.bhushan@freescale.com: reworked patch]
      Signed-off-by: default avatarBharat Bhushan <bharat.bhushan@freescale.com>
      [agraf: adjust to new request framework]
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f61c94bb
  4. 08 Apr, 2012 2 commits
  5. 05 Mar, 2012 4 commits
  6. 27 Dec, 2011 1 commit
  7. 31 Oct, 2011 1 commit
  8. 12 Jul, 2011 5 commits
    • Paul Mackerras's avatar
      KVM: PPC: Deliver program interrupts right away instead of queueing them · 3cf658b6
      Paul Mackerras authored
      
      
      Doing so means that we don't have to save the flags anywhere and gets
      rid of the last reference to to_book3s(vcpu) in arch/powerpc/kvm/book3s.c.
      
      Doing so is OK because a program interrupt won't be generated at the
      same time as any other synchronous interrupt.  If a program interrupt
      and an asynchronous interrupt (external or decrementer) are generated
      at the same time, the program interrupt will be delivered, which is
      correct because it has a higher priority, and then the asynchronous
      interrupt will be masked.
      
      We don't ever generate system reset or machine check interrupts to the
      guest, but if we did, then we would need to make sure they got delivered
      rather than the program interrupt.  The current code would be wrong in
      this situation anyway since it would deliver the program interrupt as
      well as the reset/machine check interrupt.
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      3cf658b6
    • Paul Mackerras's avatar
      KVM: PPC: Split out code from book3s.c into book3s_pr.c · f05ed4d5
      Paul Mackerras authored
      
      
      In preparation for adding code to enable KVM to use hypervisor mode
      on 64-bit Book 3S processors, this splits book3s.c into two files,
      book3s.c and book3s_pr.c, where book3s_pr.c contains the code that is
      specific to running the guest in problem state (user mode) and book3s.c
      contains code which should apply to all Book 3S processors.
      
      In doing this, we abstract some details, namely the interrupt offset,
      updating the interrupt pending flag, and detecting if the guest is
      in a critical section.  These are all things that will be different
      when we use hypervisor mode.
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f05ed4d5
    • Paul Mackerras's avatar
      KVM: PPC: Move fields between struct kvm_vcpu_arch and kvmppc_vcpu_book3s · c4befc58
      Paul Mackerras authored
      
      
      This moves the slb field, which represents the state of the emulated
      SLB, from the kvmppc_vcpu_book3s struct to the kvm_vcpu_arch, and the
      hpte_hash_[v]pte[_long] fields from kvm_vcpu_arch to kvmppc_vcpu_book3s.
      This is in accord with the principle that the kvm_vcpu_arch struct
      represents the state of the emulated CPU, and the kvmppc_vcpu_book3s
      struct holds the auxiliary data structures used in the emulation.
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      c4befc58
    • Paul Mackerras's avatar
      KVM: PPC: Fix machine checks on 32-bit Book3S · 149dbdb1
      Paul Mackerras authored
      
      
      Commit 69acc0d3ba ("KVM: PPC: Resolve real-mode handlers through
      function exports") resulted in vcpu->arch.trampoline_lowmem and
      vcpu->arch.trampoline_enter ending up with kernel virtual addresses
      rather than physical addresses.  This is OK on 64-bit Book3S machines,
      which ignore the top 4 bits of the effective address in real mode,
      but on 32-bit Book3S machines, accessing these addresses in real mode
      causes machine check interrupts, as the hardware uses the whole
      effective address as the physical address in real mode.
      
      This fixes the problem by using __pa() to convert these addresses
      to physical addresses.
      
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      149dbdb1
    • Alexander Graf's avatar
      KVM: PPC: Resolve real-mode handlers through function exports · a22a2dac
      Alexander Graf authored
      
      
      Up until now, Book3S KVM had variables stored in the kernel that a kernel module
      or the kvm code in the kernel could read from to figure out where some real mode
      helper functions are located.
      
      This is all unnecessary. The high bits of the EA get ignore in real mode, so we
      can just use the pointer as is. Also, it's a lot easier on relocations when we
      use the normal way of resolving the address to a function, instead of jumping
      through hoops.
      
      This patch fixes compilation with CONFIG_RELOCATABLE=y.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      a22a2dac
  9. 20 May, 2011 1 commit
  10. 17 Mar, 2011 1 commit
  11. 12 Jan, 2011 1 commit
  12. 24 Oct, 2010 19 commits
    • Alexander Graf's avatar
      KVM: PPC: Implement Level interrupts on Book3S · 17bd1580
      Alexander Graf authored
      
      
      The current interrupt logic is just completely broken. We get a notification
      from user space, telling us that an interrupt is there. But then user space
      expects us that we just acknowledge an interrupt once we deliver it to the
      guest.
      
      This is not how real hardware works though. On real hardware, the interrupt
      controller pulls the external interrupt line until it gets notified that the
      interrupt was received.
      
      So in reality we have two events: pulling and letting go of the interrupt line.
      
      To maintain backwards compatibility, I added a new request for the pulling
      part. The letting go part was implemented earlier already.
      
      With this in place, we can now finally start guests that do not randomly stall
      and stop to work at random times.
      
      This patch implements above logic for Book3S.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      17bd1580
    • Alexander Graf's avatar
      KVM: PPC: Don't put MSR_POW in MSR · 296c19d0
      Alexander Graf authored
      
      
      On Book3S a mtmsr with the MSR_POW bit set indicates that the OS is in
      idle and only needs to be waked up on the next interrupt.
      
      Now, unfortunately we let that bit slip into the stored MSR value which
      is not what the real CPU does, so that we ended up executing code like
      this:
      
      	r = mfmsr();
      	/* r containts MSR_POW */
      	mtmsr(r | MSR_EE);
      
      This obviously breaks, as we're going into idle mode in code sections that
      don't expect to be idling.
      
      This patch masks MSR_POW out of the stored MSR value on wakeup, making
      guests happy again.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      296c19d0
    • Alexander Graf's avatar
      KVM: PPC: Update int_pending also on dequeue · 9ee18b1e
      Alexander Graf authored
      
      
      When having a decrementor interrupt pending, the dequeuing happens manually
      through an mtdec instruction. This instruction simply calls dequeue on that
      interrupt, so the int_pending hint doesn't get updated.
      
      This patch enables updating the int_pending hint also on dequeue, thus
      correctly enabling guests to stay in guest contexts more often.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      9ee18b1e
    • Alexander Graf's avatar
      KVM: PPC: Put segment registers in shared page · df1bfa25
      Alexander Graf authored
      
      
      Now that the actual mtsr doesn't do anything anymore, we can move the sr
      contents over to the shared page, so a guest can directly read and write
      its sr contents from guest context.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      df1bfa25
    • Alexander Graf's avatar
      KVM: PPC: Interpret SR registers on demand · 8e865178
      Alexander Graf authored
      
      
      Right now we're examining the contents of Book3s_32's segment registers when
      the register is written and put the interpreted contents into a struct.
      
      There are two reasons this is bad. For starters, the struct has worse real-time
      performance, as it occupies more ram. But the more important part is that with
      segment registers being interpreted from their raw values, we can put them in
      the shared page, allowing guests to mess with them directly.
      
      This patch makes the internal representation of SRs be u32s.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      8e865178
    • Alexander Graf's avatar
      KVM: PPC: Don't flush PTEs on NX/RO hit · 2e602847
      Alexander Graf authored
      
      
      When hitting a no-execute or read-only data/inst storage interrupt we were
      flushing the respective PTE so we're sure it gets properly overwritten next.
      
      According to the spec, this is unnecessary though. The guest issues a tlbie
      anyways, so we're safe to just keep the PTE around and have it manually removed
      from the guest, saving us a flush.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      2e602847
    • Alexander Graf's avatar
      KVM: PPC: Preload magic page when in kernel mode · 4cb6b7ea
      Alexander Graf authored
      
      
      When the guest jumps into kernel mode and has the magic page mapped, theres a
      very high chance that it will also use it. So let's detect that scenario and
      map the segment accordingly.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      4cb6b7ea
    • Alexander Graf's avatar
      KVM: PPC: Move EXIT_DEBUG partially to tracepoints · bed1ed98
      Alexander Graf authored
      
      
      We have a debug printk on every exit that is usually #ifdef'ed out. Using
      tracepoints makes a lot more sense here though, as they can be dynamically
      enabled.
      
      This patch converts the most commonly used debug printks of EXIT_DEBUG to
      tracepoints.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      bed1ed98
    • Wei Yongjun's avatar
      KVM: PPC: fix leakage of error page in kvmppc_patch_dcbz() · 646bab55
      Wei Yongjun authored
      
      
      Add kvm_release_page_clean() after is_error_page() to avoid
      leakage of error page.
      
      Signed-off-by: default avatarWei Yongjun <yjwei@cn.fujitsu.com>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      646bab55
    • Alexander Graf's avatar
      KVM: PPC: Magic Page Book3s support · e8508940
      Alexander Graf authored
      
      
      We need to override EA as well as PA lookups for the magic page. When the guest
      tells us to project it, the magic page overrides any guest mappings.
      
      In order to reflect that, we need to hook into all the MMU layers of KVM to
      force map the magic page if necessary.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      e8508940
    • Alexander Graf's avatar
      KVM: PPC: Make PAM a define · 28e83b4f
      Alexander Graf authored
      
      
      On PowerPC it's very normal to not support all of the physical RAM in real mode.
      To check if we're matching on the shared page or not, we need to know the limits
      so we can restrain ourselves to that range.
      
      So let's make it a define instead of open-coding it. And while at it, let's also
      increase it.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      
      v2 -> v3:
      
        - RMO -> PAM (non-magic page)
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      28e83b4f
    • Alexander Graf's avatar
      KVM: PPC: Tell guest about pending interrupts · 90bba358
      Alexander Graf authored
      
      
      When the guest turns on interrupts again, it needs to know if we have an
      interrupt pending for it. Because if so, it should rather get out of guest
      context and get the interrupt.
      
      So we introduce a new field in the shared page that we use to tell the guest
      that there's a pending interrupt lying around.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      90bba358
    • Alexander Graf's avatar
      KVM: PPC: Add PV guest critical sections · 5c6cedf4
      Alexander Graf authored
      
      
      When running in hooked code we need a way to disable interrupts without
      clobbering any interrupts or exiting out to the hypervisor.
      
      To achieve this, we have an additional critical field in the shared page. If
      that field is equal to the r1 register of the guest, it tells the hypervisor
      that we're in such a critical section and thus may not receive any interrupts.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      5c6cedf4
    • Alexander Graf's avatar
      KVM: PPC: Implement hypervisor interface · 2a342ed5
      Alexander Graf authored
      
      
      To communicate with KVM directly we need to plumb some sort of interface
      between the guest and KVM. Usually those interfaces use hypercalls.
      
      This hypercall implementation is described in the last patch of the series
      in a special documentation file. Please read that for further information.
      
      This patch implements stubs to handle KVM PPC hypercalls on the host and
      guest side alike.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      2a342ed5
    • Alexander Graf's avatar
      KVM: PPC: Convert SPRG[0-4] to shared page · a73a9599
      Alexander Graf authored
      
      
      When in kernel mode there are 4 additional registers available that are
      simple data storage. Instead of exiting to the hypervisor to read and
      write those, we can just share them with the guest using the page.
      
      This patch converts all users of the current field to the shared page.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      a73a9599
    • Alexander Graf's avatar
      KVM: PPC: Convert SRR0 and SRR1 to shared page · de7906c3
      Alexander Graf authored
      
      
      The SRR0 and SRR1 registers contain cached values of the PC and MSR
      respectively. They get written to by the hypervisor when an interrupt
      occurs or directly by the kernel. They are also used to tell the rfi(d)
      instruction where to jump to.
      
      Because it only gets touched on defined events that, it's very simple to
      share with the guest. Hypervisor and guest both have full r/w access.
      
      This patch converts all users of the current field to the shared page.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      de7906c3
    • Alexander Graf's avatar
      KVM: PPC: Convert DAR to shared page. · 5e030186
      Alexander Graf authored
      
      
      The DAR register contains the address a data page fault occured at. This
      register behaves pretty much like a simple data storage register that gets
      written to on data faults. There is no hypervisor interaction required on
      read or write.
      
      This patch converts all users of the current field to the shared page.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      5e030186
    • Alexander Graf's avatar
      KVM: PPC: Convert DSISR to shared page · d562de48
      Alexander Graf authored
      
      
      The DSISR register contains information about a data page fault. It is fully
      read/write from inside the guest context and we don't need to worry about
      interacting based on writes of this register.
      
      This patch converts all users of the current field to the shared page.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      d562de48
    • Alexander Graf's avatar
      KVM: PPC: Convert MSR to shared page · 666e7252
      Alexander Graf authored
      
      
      One of the most obvious registers to share with the guest directly is the
      MSR. The MSR contains the "interrupts enabled" flag which the guest has to
      toggle in critical sections.
      
      So in order to bring the overhead of interrupt en- and disabling down, let's
      put msr into the shared page. Keep in mind that even though you can fully read
      its contents, writing to it doesn't always update all state. There are a few
      safe fields that don't require hypervisor interaction. See the documentation
      for a list of MSR bits that are safe to be set from inside the guest.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
      666e7252