1. 19 Dec, 2016 1 commit
  2. 29 Nov, 2016 11 commits
  3. 18 Nov, 2016 1 commit
  4. 16 Nov, 2016 1 commit
  5. 20 Oct, 2016 2 commits
  6. 19 Oct, 2016 1 commit
  7. 17 Oct, 2016 1 commit
    • Marc Zyngier's avatar
      irqchip/gic-v3-its: Fix 64bit GIC{R,ITS}_TYPER accesses · 589ce5f4
      Marc Zyngier authored
      The GICv3 architecture specification mentions that a 64bit
      register can be accessed using two 32bit accesses. What it
      doesn't mention is that this is only guaranteed on a system
      that implements AArch32, and a pure AArch64 system is allowed
      not to support this. This causes issues with the GICR_TYPER
      and GITS_TYPER registers, which are both RO 64bit registers.
      In order to solve this, this patch switches the TYPER accesses
      to the gic_read_typer macro already used in other parts of the
      driver. This makes sure that we always use a 64bit access on
      64bit systems, and two 32bit accesses on 32bit system.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  8. 14 Oct, 2016 3 commits
  9. 11 Oct, 2016 1 commit
  10. 06 Oct, 2016 3 commits
  11. 05 Oct, 2016 2 commits
  12. 21 Sep, 2016 1 commit
  13. 20 Sep, 2016 2 commits
    • Paul Burton's avatar
      irqchip/mips-gic: Use for_each_set_bit to iterate over local IRQs · 0f4ed158
      Paul Burton authored
      The MIPS GIC driver has previously iterated over bits set in a bitmap
      representing pending local IRQs by calling find_first_bit, clearing that
      bit then calling find_first_bit again until all bits are clear. If
      multiple interrupts are pending then this is wasteful, as find_first_bit
      will have to loop over the whole bitmap from the start. Use the
      for_each_set_bit macro which performs exactly what we need here instead.
      It will use find_next_bit and thus only scan over the relevant part of
      the bitmap, and it makes the intent of the code clearer.
      This makes the same change for local interrupts that commit cae750ba
      ("irqchip: mips-gic: Use for_each_set_bit to iterate over IRQs") made
      for shared interrupts.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/20160913165427.31686-1-paul.burton@imgtec.com
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    • Paul Burton's avatar
      irqchip/mips-gic: Fix local interrupts · e875bd66
      Paul Burton authored
      Since the device hierarchy domain was added by commit c98c1822
      ("irqchip/mips-gic: Add device hierarchy domain"), GIC local interrupts
      have been broken.
      Users attempting to setup a per-cpu local IRQ, for example the GIC timer
      clock events code in drivers/clocksource/mips-gic-timer.c, the
      setup_percpu_irq function would refuse with -EINVAL because the GIC
      irqchip driver never called irq_set_percpu_devid so the
      IRQ_PER_CPU_DEVID flag was never set for the IRQ. This happens because
      irq_set_percpu_devid was being called from the gic_irq_domain_map
      function which is no longer called.
      Doing only that runs into further problems because gic_dev_domain_alloc
      set the struct irq_chip for all interrupts, local or shared, to
      gic_level_irq_controller despite that only being suitable for shared
      interrupts. The typical outcome of this is that gic_level_irq_controller
      callback functions are called for local interrupts, and then hwirq
      number calculations overflow & the driver ends up attempting to access
      some invalid register with an address calculated from an invalid hwirq
      number. Best case scenario is that this then leads to a bus error. This
      is fixed by abstracting the setup of the hwirq & chip to a new function
      gic_setup_dev_chip which is used by both the root GIC IRQ domain & the
      device domain.
      Finally, decoding local interrupts failed because gic_dev_domain_alloc
      only called irq_domain_alloc_irqs_parent for shared interrupts. Local
      ones were therefore never associated with hwirqs in the root GIC IRQ
      domain and the virq in gic_handle_local_int would always be 0. This is
      fixed by calling irq_domain_alloc_irqs_parent unconditionally & having
      gic_irq_domain_alloc handle both local & shared interrupts, which is
      easy due to the aforementioned abstraction of chip setup into
      This fixes use of the MIPS GIC timer for clock events, which has been
      broken since c98c1822 ("irqchip/mips-gic: Add device hierarchy
      domain") but hadn't been noticed due to a silent fallback to the MIPS
      coprocessor 0 count/compare clock events device.
      Fixes: c98c1822
       ("irqchip/mips-gic: Add device hierarchy domain")
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Qais Yousef <qsyousef@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Link: http://lkml.kernel.org/r/20160913165335.31389-1-paul.burton@imgtec.com
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  14. 19 Sep, 2016 1 commit
    • James Morse's avatar
      irqchip/gicv3: Silence noisy DEBUG_PER_CPU_MAPS warning · 727653d6
      James Morse authored
      gic_raise_softirq() walks the list of cpus using for_each_cpu(), it calls
      gic_compute_target_list() which advances the iterator by the number of
      CPUs in the cluster.
      If gic_compute_target_list() reaches the last CPU it leaves the iterator
      pointing at the last CPU. This means the next time round the for_each_cpu()
      loop cpumask_next() will be called with an invalid CPU.
      This triggers a warning when built with CONFIG_DEBUG_PER_CPU_MAPS:
      [    3.077738] GICv3: CPU1: found redistributor 1 region 0:0x000000002f120000
      [    3.077943] CPU1: Booted secondary processor [410fd0f0]
      [    3.078542] ------------[ cut here ]------------
      [    3.078746] WARNING: CPU: 1 PID: 0 at ../include/linux/cpumask.h:121 gic_raise_softirq+0x12c/0x170
      [    3.078812] Modules linked in:
      [    3.078869]
      [    3.078930] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0-rc5+ #5188
      [    3.078994] Hardware name: Foundation-v8A (DT)
      [    3.079059] task: ffff80087a1a0080 task.stack: ffff80087a19c000
      [    3.079145] PC is at gic_raise_softirq+0x12c/0x170
      [    3.079226] LR is at gic_raise_softirq+0xa4/0x170
      [    3.079296] pc : [<ffff0000083ead24>] lr : [<ffff0000083eac9c>] pstate: 200001c9
      [    3.081139] Call trace:
      [    3.081202] Exception stack(0xffff80087a19fbe0 to 0xffff80087a19fd10)
      [    3.082269] [<ffff0000083ead24>] gic_raise_softirq+0x12c/0x170
      [    3.082354] [<ffff00000808e614>] smp_send_reschedule+0x34/0x40
      [    3.082433] [<ffff0000080e80a0>] resched_curr+0x50/0x88
      [    3.082512] [<ffff0000080e89d0>] check_preempt_curr+0x60/0xd0
      [    3.082593] [<ffff0000080e8a60>] ttwu_do_wakeup+0x20/0xe8
      [    3.082672] [<ffff0000080e8bb8>] ttwu_do_activate+0x90/0xc0
      [    3.082753] [<ffff0000080ea9a4>] try_to_wake_up+0x224/0x370
      [    3.082836] [<ffff0000080eabc8>] default_wake_function+0x10/0x18
      [    3.082920] [<ffff000008103134>] __wake_up_common+0x5c/0xa0
      [    3.083003] [<ffff0000081031f4>] __wake_up_locked+0x14/0x20
      [    3.083086] [<ffff000008103f80>] complete+0x40/0x60
      [    3.083168] [<ffff00000808df7c>] secondary_start_kernel+0x15c/0x1d0
      [    3.083240] [<00000000808911a4>] 0x808911a4
      [    3.113401] Detected PIPT I-cache on CPU2
      Avoid updating the iterator if the next call to cpumask_next() would
      cause the for_each_cpu() loop to exit.
      There is no change to gic_raise_softirq()'s behaviour, (cpumask_next()s
      eventual call to _find_next_bit() will return early as start >= nbits),
      this patch just silences the warning.
      Fixes: 021f6537
       ("irqchip: gic-v3: Initial support for GICv3")
      Signed-off-by: default avatarJames Morse <james.morse@arm.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1474306155-3303-1-git-send-email-james.morse@arm.com
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
  15. 16 Sep, 2016 1 commit
  16. 13 Sep, 2016 1 commit
  17. 12 Sep, 2016 7 commits