1. 07 Jun, 2016 1 commit
  2. 01 Jun, 2016 1 commit
  3. 25 May, 2016 1 commit
  4. 23 May, 2016 2 commits
  5. 19 Apr, 2016 1 commit
  6. 28 Mar, 2016 2 commits
    • Philippe Gerum's avatar
      ipipe-core-4.1.18-arm-4 · 07982ac5
      Philippe Gerum authored
      07982ac5
    • Philippe Gerum's avatar
      arm/mm: l2x0: allow for disabling write-allocate · dff9061b
      Philippe Gerum authored
      
      
      Re-introduce a config switch (l2x0_write_allocate=) for controlling
      the write-allocate policy. Such policy is known to induce very high
      latencies: it typically doubles the worst-case figures on imx6q (PL310
      cache controller).
      
      By default, the default policy is usually determined by the AWCACHE
      attribute settings unless the platform code forced it in the auxiliary
      control register. In the common case, write allocation is selected.
      
      The patch applies to L310 and L220 cache controllers exclusively:
      
      - if l2x0_write_allocate= is not set, turn write allocation off.
      
      - if write allocation ends up being enabled, warn about expected high
        latencies.
      Signed-off-by: default avatarGilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
      Signed-off-by: Philippe Gerum's avatarPhilippe Gerum <rpm@xenomai.org>
      dff9061b
  7. 25 Mar, 2016 1 commit
    • Philippe Gerum's avatar
      arm/ipipe: gpc: fix two stage unlocking in mask/unmask · 3630835f
      Philippe Gerum authored
      (raw_)spin_lock_irqsave() on hard I-pipe locks encodes the virtual IRQ
      state in the flags returned, using bit #8 (PSR_A) to reflect the
      current STALL bit state. Therefore such flags may not be passed to the
      hard_local_irq*() interface directly.
      
      Use the __ipipe_spin_unlock_irqbegin/complete() API for this.
      3630835f
  8. 24 Mar, 2016 9 commits
  9. 13 Mar, 2016 5 commits
  10. 02 Mar, 2016 2 commits
  11. 29 Feb, 2016 1 commit
  12. 28 Feb, 2016 14 commits