1. 09 Jul, 2016 4 commits
    • Philippe Gerum's avatar
      ipipe-core-4.1.18-arm-6 · c61d7aed
      Philippe Gerum authored
    • Philippe Gerum's avatar
      ipipe: fix bad reference to invalid percpu data · a648a316
      Philippe Gerum authored
      Since debug_smp_processor_id() can be called very early during the
      boot process when CONFIG_DEBUG_PREEMPT is enabled, testing
      ipipe_root_p() may be invalid on architectures with late percpu memory
      fixups such as ppc64.
      Prevent bad references to invalid percpu memory by checking for
      disabled hard IRQs first, which denotes a non-preemptible context, and
      always evaluates to true during the early boot phase mentioned above.
    • Philippe Gerum's avatar
    • Philippe Gerum's avatar
      powerpc/ipipe: book3s: don't trash stall bit on return from exception · c1ff97e0
      Philippe Gerum authored
      When the pipeline is enabled, the stall bit denotes the current
      interrupt state. On the other hand, pt_regs->SOFTE only reflects the
      stall bit state on entry of an exception context.
      Therefore we should not copy SOFTE back to the stall bit when
      returning from exception; the fix drops that part. However we must
      mirror the stall bit into SOFTE when entering an exception context
      (which we already do properly).
  2. 05 Jul, 2016 5 commits
  3. 20 Jun, 2016 3 commits
    • Gilles Chanteperdrix's avatar
      ipipe: fixup genpatches script · 5352f2e4
      Gilles Chanteperdrix authored
    • Gilles Chanteperdrix's avatar
      arm/ipipe: forbid UACCESS_WITH_MEMCPY · 7056fb83
      Gilles Chanteperdrix authored
      The implementation of copy to/from user-space with memcpy requires
      pinning the user-space pages and holding the page table spinlock.
      Enabling this option with I-pipe debug option results in the following
      trace during the execution of the mutex-torture-native unit test:
      [  146.850000] I-pipe: Detected illicit call from head domain 'Xenomai'
      [  146.850000]         into a regular Linux service
      [  146.850000] CPU: 0 PID: 760 Comm: main_task Not tainted 3.18.20-ipipe
      [  146.850000] [<c0011fb9>] (unwind_backtrace) from [<c00100fd>]
      [  146.850000] [<c00100fd>] (show_stack) from [<c00557d5>]
      [  146.850000] [<c00557d5>] (ipipe_root_only) from [<c002e83f>]
      [  146.850000] [<c002e83f>] (preempt_count_add) from [<c0442309>]
      [  146.850000] [<c0442309>] (_raw_spin_lock) from [<c020e911>]
      [  146.850000] [<c020e911>] (pin_page_for_write) from [<c020e999>]
      [  146.850000] [<c020e999>] (__copy_to_user_memcpy) from [<c0099e61>]
      [  146.850000] [<c0099e61>] (__rt_task_inquire) from [<c0083cfd>]
      [  146.850000] [<c0083cfd>] (hisyscall_event) from [<c00568ab>]
      [  146.850000] [<c00568ab>] (__ipipe_notify_syscall) from [<c000d6e9>]
      [  146.850000] [<c000d6e9>] (pipeline_syscall) from [<bed2ebc8>]
    • Gilles Chanteperdrix's avatar
  4. 17 Jun, 2016 1 commit
    • Gilles Chanteperdrix's avatar
      ipipe/x86: export missing symbols · 4ac08725
      Gilles Chanteperdrix authored
      When Xenomai 2.x is compiled as a module, and tracepoints are enabled,
      the tlb_flush tracepoint gets called during context switches. Export it.
      rdpmc_always_available must also be exported when PERF_EVENTS is
  5. 07 Jun, 2016 1 commit
  6. 01 Jun, 2016 1 commit
  7. 25 May, 2016 1 commit
  8. 23 May, 2016 2 commits
  9. 19 Apr, 2016 1 commit
  10. 28 Mar, 2016 2 commits
    • Philippe Gerum's avatar
      ipipe-core-4.1.18-arm-4 · 07982ac5
      Philippe Gerum authored
    • Philippe Gerum's avatar
      arm/mm: l2x0: allow for disabling write-allocate · dff9061b
      Philippe Gerum authored
      Re-introduce a config switch (l2x0_write_allocate=) for controlling
      the write-allocate policy. Such policy is known to induce very high
      latencies: it typically doubles the worst-case figures on imx6q (PL310
      cache controller).
      By default, the default policy is usually determined by the AWCACHE
      attribute settings unless the platform code forced it in the auxiliary
      control register. In the common case, write allocation is selected.
      The patch applies to L310 and L220 cache controllers exclusively:
      - if l2x0_write_allocate= is not set, turn write allocation off.
      - if write allocation ends up being enabled, warn about expected high
      Signed-off-by: default avatarGilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
      Signed-off-by: Philippe Gerum's avatarPhilippe Gerum <rpm@xenomai.org>
  11. 25 Mar, 2016 1 commit
    • Philippe Gerum's avatar
      arm/ipipe: gpc: fix two stage unlocking in mask/unmask · 3630835f
      Philippe Gerum authored
      (raw_)spin_lock_irqsave() on hard I-pipe locks encodes the virtual IRQ
      state in the flags returned, using bit #8 (PSR_A) to reflect the
      current STALL bit state. Therefore such flags may not be passed to the
      hard_local_irq*() interface directly.
      Use the __ipipe_spin_unlock_irqbegin/complete() API for this.
  12. 24 Mar, 2016 9 commits
  13. 13 Mar, 2016 5 commits
  14. 02 Mar, 2016 2 commits
  15. 29 Feb, 2016 1 commit
  16. 28 Feb, 2016 1 commit