1. 10 Oct, 2008 2 commits
  2. 09 Oct, 2008 1 commit
  3. 08 Oct, 2008 1 commit
  4. 06 Oct, 2008 4 commits
  5. 05 Oct, 2008 5 commits
  6. 03 Oct, 2008 11 commits
  7. 02 Oct, 2008 1 commit
  8. 01 Oct, 2008 2 commits
    • David Howells's avatar
      MN10300: Fix IRQ handling · d6478fad
      David Howells authored
      
      
      Fix the IRQ handling on the MN10300 arch.
      
      This patch makes a number of significant changes:
      
       (1) It separates the irq_chip definition for edge-triggered interrupts from
           the one for level-triggered interrupts.
      
           This is necessary because the MN10300 PIC latches the IRQ channel's
           interrupt request bit (GxICR_REQUEST), even after the device has ceased to
           assert its interrupt line and the interrupt channel has been disabled in
           the PIC.  So for level-triggered interrupts we need to clear this bit when
           we re-enable - which is achieved by setting GxICR_DETECT but not
           GxICR_REQUEST when writing to the register.
      
           Not doing this results in spurious interrupts occurring because calling
           mask_ack() at the start of handle_level_irq() is insufficient - it fails
           to clear the REQUEST latch because the device that caused the interrupt is
           still asserting its interrupt line at this point.
      
       (2) IRQ disablement [irq_chip::disable_irq()] shouldn't clear the interrupt
           request flag for edge-triggered interrupts lest it lose an interrupt.
      
       (3) IRQ unmasking [irq_chip::unmask_irq()] also shouldn't clear the interrupt
           request flag for edge-triggered interrupts lest it lose an interrupt.
      
       (4) The end() operation is now left to the default (no-operation) as
           __do_IRQ() is compiled out.  This may affect misrouted_irq(), but
           according to Thomas Gleixner it's the correct thing to do.
      
       (5) handle_level_irq() is used for edge-triggered interrupts rather than
           handle_edge_irq() as the MN10300 PIC latches interrupt events even on
           masked IRQ channels, thus rendering IRQ_PENDING unnecessary.  It is
           sufficient to call mask_ack() at the start and unmask() at the end.
      
       (6) For level-triggered interrupts, ack() is now NULL as it's not used, and
           there is no effective ACK function on the PIC.  mask_ack() is now the
           same as mask() as the latch continues to latch, even when the channel is
           masked.
      
      Further, the patch discards the disable() op implementation as its now the same
      as the mask() op implementation, which is used instead.
      
      It also discards the enable() op implementations as they're now the same as
      the unmask() op implementations, which are used instead.
      Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      d6478fad
    • Yinghai Lu's avatar
      x86: change MTRR_SANITIZER to def_bool y · 2ffb3501
      Yinghai Lu authored
      This option has been added in v2.6.26 as a default-disabled
      feature and went through several revisions since then.
      
      The feature fixes a wide range of MTRR setup problems that BIOSes
      leave us with: slow system, slow Xorg, slow system when adding lots
      of RAM, etc., so we want to enable it by default for v2.6.28.
      
      See:
      
        [Bug 10508] Upgrade to 4GB of RAM messes up MTRRs
        http://bugzilla.kernel.org/show_bug.cgi?id=10508
      
      and the test results in:
      
         http://lkml.org/lkml/2008/9/29/273
      
      
      
      1. hpa
      reg00: base=0xc0000000 (3072MB), size=1024MB: uncachable, count=1
      reg01: base=0x13c000000 (5056MB), size=  64MB: uncachable, count=1
      reg02: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
      reg03: base=0x100000000 (4096MB), size=1024MB: write-back, count=1
      reg04: base=0xbf700000 (3063MB), size=   1MB: uncachable, count=1
      reg05: base=0xbf800000 (3064MB), size=   8MB: uncachable, count=1
      
      will get
      Found optimal setting for mtrr clean up
      gran_size: 1M   chunk_size: 128M        num_reg: 6      lose RAM: 0M
      range0: 0000000000000000 - 00000000c0000000
      Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
      Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
      hole: 00000000bf700000 - 00000000c0000000
      Setting variable MTRR 2, base: 3063MB, range: 1MB, type UC
      Setting variable MTRR 3, base: 3064MB, range: 8MB, type UC
      range0: 0000000100000000 - 0000000140000000
      Setting variable MTRR 4, base: 4096MB, range: 1024MB, type WB
      hole: 000000013c000000 - 0000000140000000
      Setting variable MTRR 5, base: 5056MB, range: 64MB, type UC
      
      2. Dylan Taft
      reg00: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
      reg01: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
      reg02: base=0x120000000 (4608MB), size= 256MB: write-back, count=1
      reg03: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
      reg04: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
      reg05: base=0xc7e00000 (3198MB), size=   2MB: uncachable, count=1
      reg06: base=0xc8000000 (3200MB), size= 128MB: uncachable, count=1
      
      will get
      Found optimal setting for mtrr clean up
      gran_size: 1M   chunk_size: 4M  num_reg: 6      lose RAM: 0M
      range0: 0000000000000000 - 00000000c8000000
      Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
      Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
      Setting variable MTRR 2, base: 3072MB, range: 128MB, type WB
      hole: 00000000c7e00000 - 00000000c8000000
      Setting variable MTRR 3, base: 3198MB, range: 2MB, type UC
      rangeX: 0000000100000000 - 0000000130000000
      Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
      Setting variable MTRR 5, base: 4608MB, range: 256MB, type WB
      
      3. Gabriel
      reg00: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
      reg01: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
      reg02: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
      reg03: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
      reg04: base=0x120000000 (4608MB), size= 128MB: write-back, count=1
      reg05: base=0x128000000 (4736MB), size=  64MB: write-back, count=1
      reg06: base=0xcf600000 (3318MB), size=   2MB: uncachable, count=1
      
      will get
      Found optimal setting for mtrr clean up
      gran_size: 1M   chunk_size: 16M         num_reg: 7      lose RAM: 0M
      range0: 0000000000000000 - 00000000d0000000
      Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
      Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
      Setting variable MTRR 2, base: 3072MB, range: 256MB, type WB
      hole: 00000000cf600000 - 00000000cf800000
      Setting variable MTRR 3, base: 3318MB, range: 2MB, type UC
      rangeX: 0000000100000000 - 000000012c000000
      Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
      Setting variable MTRR 5, base: 4608MB, range: 128MB, type WB
      Setting variable MTRR 6, base: 4736MB, range: 64MB, type WB
      
      4. Mika Fischer
      reg00: base=0xc0000000 (3072MB), size=1024MB: uncachable, count=1
      reg01: base=0x00000000 ( 0MB), size=4096MB: write-back, count=1
      reg02: base=0x100000000 (4096MB), size=1024MB: write-back, count=1
      reg03: base=0xbf700000 (3063MB), size= 1MB: uncachable, count=1
      reg04: base=0xbf800000 (3064MB), size= 8MB: uncachable, count=1
      
      will get
      Found optimal setting for mtrr clean up
      gran_size: 1M   chunk_size: 16M         num_reg: 5      lose RAM: 0M
      range0: 0000000000000000 - 00000000c0000000
      Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
      Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
      hole: 00000000bf700000 - 00000000c0000000
      Setting variable MTRR 2, base: 3063MB, range: 1MB, type UC
      Setting variable MTRR 3, base: 3064MB, range: 8MB, type UC
      rangeX: 0000000100000000 - 0000000140000000
      Setting variable MTRR 4, base: 4096MB, range: 1024MB, type WB
      Signed-off-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2ffb3501
  9. 30 Sep, 2008 10 commits
  10. 29 Sep, 2008 2 commits
  11. 28 Sep, 2008 1 commit