1. 12 Jan, 2006 1 commit
  2. 30 Sep, 2005 1 commit
  3. 29 Sep, 2005 3 commits
  4. 26 Sep, 2005 1 commit
    • David S. Miller's avatar
      [SPARC64]: Probe D/I/E-cache config and use. · 80dc0d6b
      David S. Miller authored
      
      
      At boot time, determine the D-cache, I-cache and E-cache size and
      line-size.  Use them in cache flushes when appropriate.
      
      This change was motivated by discovering that the D-cache on
      UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
      Cheetah error handlers were assuming a 32K size.
      
      There are still some pieces of code that are hard coding things and
      will need to be fixed up at some point.
      
      While we're here, fix the D-cache and I-cache parity error handlers
      to run with interrupts disabled, and when the trap occurs at trap
      level > 1 log the event via a counter displayed in /proc/cpuinfo.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      80dc0d6b
  5. 29 Aug, 2005 2 commits
    • David S. Miller's avatar
      [SPARC64]: Revamp Spitfire error trap handling. · 6c52a96e
      David S. Miller authored
      
      
      Current uncorrectable error handling was poor enough
      that the processor could just loop taking the same
      trap over and over again.  Fix things up so that we
      at least get a log message and perhaps even some register
      state.
      
      In the process, much consolidation became possible,
      particularly with the correctable error handler.
      
      Prefix assembler and C function names with "spitfire"
      to indicate that these are for Ultra-I/II/IIi/IIe only.
      
      More work is needed to make these routines robust and
      featureful to the level of the Ultra-III error handlers.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6c52a96e
    • David S. Miller's avatar
      [SPARC64]: Do not call winfix_dax blindly · bde4e4ee
      David S. Miller authored
      
      
      Verify we really are taking a data access exception trap, at TL1, from
      one of the window spill/fill handlers.
      
      Else call a new function, data_access_exception_tl1, to log the error.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      bde4e4ee
  6. 19 Aug, 2005 1 commit
  7. 25 Jul, 2005 1 commit
  8. 23 May, 2005 1 commit
    • David S. Miller's avatar
      [SPARC64]: Add boot option to force UltraSPARC-III P-Cache on. · 816242da
      David S. Miller authored
      
      
      Older UltraSPARC-III chips have a P-Cache bug that makes us disable it
      by default at boot time.
      
      However, this does hurt performance substantially, particularly with
      memcpy(), and the bug is _incredibly_ obscure.  I have never seen it
      triggered in practice, ever.
      
      So provide a "-P" boot option that forces the P-Cache on.  It taints
      the kernel, so if it does trigger and cause some data corruption or
      OOPS, we will find out in the logs that this option was on when it
      happened.
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      816242da
  9. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4