• Maciej W. Rozycki's avatar
    MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue · 1c84d14e
    Maciej W. Rozycki authored
    [ Upstream commit 5a1aca44 ]
    Sanitize FCSR Cause bit handling, following a trail of past attempts:
    * commit 42495484 ("MIPS: ptrace: Fix FP context restoration FCSR
    * commit 443c4403 ("MIPS: Always clear FCSR cause bits after
    * commit 64bedffe ("MIPS: Clear [MSA]FPE CSR.Cause after
    * commit b1442d39 ("MIPS: Prevent user from setting FCSR cause
    * commit b54d2901517d ("Properly handle branch delay slots in connection
    with signals.").
    Specifically do not mask these bits out in ptrace(2) processing and send
    a SIGFPE signal instead whenever a matching pair of an FCSR Cause and
    Enable bit is seen as execution of an affected context is about to
    resume.  Only then clear Cause bits, and even then do not clear any bits
    that are set but masked with the respective Enable bits.  Adjust Cause
    bit clearing throughout code likewise, except within the FPU emulator
    proper where they are set according to IEEE 754 exceptions raised as the
    operation emulated executed.  Do so so that any IEEE 754 exceptions
    subject to their default handling are recorded like with operations
    executed by FPU hardware.
    Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
    Cc: Paul Burton <paul.burton@imgtec.com>
    Cc: James Hogan <james.hogan@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/14460/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
switch_to.h 3.99 KB