Commit 19ddc546 authored by Pavel Machek's avatar Pavel Machek
Browse files

Remove more parts unneccessary for NOR.

parent 96e8bf3f
/*
* Copyright Altera Corporation (C) 2012-2014. All rights reserved.
* Copyright (C) 2012 Altera <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "skeleton.dtsi"
......@@ -548,38 +549,6 @@
status = "disabled";
};
hps_0_fpgamgr: fpgamgr@0xff706000 {
compatible = "altr,fpga-mgr-1.0", "altr,fpga-mgr";
transport = "mmio";
reg = <0xFF706000 0x1000
0xFFB90000 0x1000>;
interrupts = <0 175 4>;
};
hps_fpgabridge0: fpgabridge@0 {
compatible = "altr,socfpga-hps2fpga-bridge";
label = "hps2fpga";
resets = <&rst HPS2FPGA_RESET>;
reset-names = "hps2fpga";
clocks = <&l4_main_clk>;
};
hps_fpgabridge1: fpgabridge@1 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
label = "lwhps2fpga";
resets = <&rst LWHPS2FPGA_RESET>;
reset-names = "lwhps2fpga";
clocks = <&l4_main_clk>;
};
hps_fpgabridge2: fpgabridge@2 {
compatible = "altr,socfpga-fpga2hps-bridge";
label = "fpga2hps";
resets = <&rst FPGA2HPS_RESET>;
reset-names = "fpga2hps";
clocks = <&l4_main_clk>;
};
i2c0: i2c@ffc04000 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -692,7 +661,7 @@
};
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache", "syscon";
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
interrupts = <0 38 0x04>;
cache-unified;
......@@ -714,92 +683,6 @@
clock-names = "biu", "ciu";
};
nand: nand@ff900000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "denali,denali-nand-dt";
reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 144 4>;
dma-mask = <0xffffffff>;
clocks = <&nand_clk>;
have-hw-ecc-fixup;
status = "disabled";
partition@nand-boot {
/* 8MB for raw data. */
label = "NAND Flash Boot Area 8MB";
reg = <0x0 0x800000>;
};
partition@nand-rootfs {
/* 128MB jffs2 root filesystem. */
label = "NAND Flash jffs2 Root Filesystem 128MB";
reg = <0x800000 0x8000000>;
};
partition@nand-128 {
label = "NAND Flash 128 MB";
reg = <0x8800000 0x8000000>;
};
partition@nand-64 {
label = "NAND Flash 64 MB";
reg = <0x10800000 0x4000000>;
};
partition@nand-32 {
label = "NAND Flash 32 MB";
reg = <0x14800000 0x2000000>;
};
partition@nand-16 {
label = "NAND Flash 16 MB";
reg = <0x16800000 0x1000000>;
};
};
ocram: sram@ffff0000 {
compatible = "mmio-sram";
reg = <0xffff0000 0x10000>;
};
pmu {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,cortex-a9-pmu";
interrupts = <0 176 4>, <0 177 4>;
ranges;
cti0: cti0@ff118000 {
compatible = "arm,coresight-cti";
reg = <0xff118000 0x100>;
};
cti1: cti1@ff119000 {
compatible = "arm,coresight-cti";
reg = <0xff119000 0x100>;
};
};
sdrctl@0xffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
};
l2edac@xffd08140 {
compatible = "altr,l2-edac";
reg = <0xffd08140 0x4>;
interrupts = <0 36 1>, <0 37 1>;
};
ocramedac@ffd08144 {
compatible = "altr,ocram-edac";
reg = <0xffd08144 0x4>;
iram = <&ocram>;
interrupts = <0 178 1>, <0 179 1>;
};
l3regs@0xff800000 {
compatible = "altr,l3regs", "syscon";
reg = <0xff800000 0x1000>;
};
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
......@@ -821,9 +704,7 @@
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
num-cs = <4>;
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
clocks = <&per_base_clk>;
clocks = <&spi_m_clk>;
status = "disabled";
};
......@@ -833,15 +714,13 @@
};
spi1: spi@fff01000 {
compatible = "ssnps,dw-apb-ssi";
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
interrupts = <0 156 4>;
interrupts = <0 155 4>;
num-cs = <4>;
tx-dma-channel = <&pdma 20>;
rx-dma-channel = <&pdma 21>;
clocks = <&per_base_clk>;
clocks = <&spi_m_clk>;
status = "disabled";
};
......
/*
* Copyright Altera Corporation (C) 2012,2014. All rights reserved.
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
......
/*
* Copyright Altera Corporation (C) 2012,2014. All rights reserved.
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "socfpga_cyclone5.dtsi"
......@@ -44,33 +45,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <&portb 15 1>;
};
hps1 {
label = "hps_led1";
gpios = <&portb 14 1>;
};
hps2 {
label = "hps_led2";
gpios = <&portb 13 1>;
};
hps3 {
label = "hps_led3";
gpios = <&portb 12 1>;
};
};
};
&can0 {
status = "okay";
};
&gmac1 {
......@@ -85,39 +59,14 @@
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
max-frame-size = <3800>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
speed-mode = <0>;
/*
* adjust the falling times to decrease the i2c frequency to 50Khz
* because the LCD module does not work at the standard 100Khz
*/
i2c-sda-falling-time-ns = <5000>;
i2c-scl-falling-time-ns = <5000>;
lcd: lcd@28 {
compatible = "newhaven,nhd-0216k3z-nsw-bbw";
reg = <0x28>;
height = <2>;
width = <16>;
brightness = <8>;
};
eeprom@51 {
compatible = "atmel,24c32";
......
......@@ -49,7 +49,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += reset/
# default.
obj-y += tty/
obj-y += char/
obj-$(CONFIG_FPGA) += fpga/
# iommu/ comes before gpu as gpu are using iommu controllers
obj-$(CONFIG_IOMMU_SUPPORT) += iommu/
......
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