As usual a bit late a couple of tiny fixes and improvements for ARC. 1. Switch from ARC UART to a convenient DW UART on ARC simulation platforms. This became avaialble when nSIM got support of that much more standard UART (starting from nSIM v2019.06). FWIW also available now in Free nSIM [1]. This among other things allows us finally to use the same one binary on all our simulators & FPGA-based emulators. 2. Disable networking support on simulated platforms as there's no network interface in them. 3. Add Virtio net & block devices for the configuration supported by QEMU so that we may leverage those virtual peripherals and in fact it's possible to load uImage from TFTP server and bootm it. 4. Minor fixes for HSDK clocks. 5. Rework of how we chose and use compiler options for ARC-based boards. In real world ARC-based designs are customized more or less but very rarely match any of our "templates" thus it makes not much sense to pretend we have some fixed configs, instead we now will fully reply on a SoC or even board on getting precise set of compiler options preferably even extracted from real HW via "tcfgen" utility. 6. Well and finally yet another simplification - switch to generic written in C accessors which are much more universal and just work for any target supported by the complier as compared to GAS implementation which is much more target-dependent. This one was heavily "inspired" by similar implementation for RISCV and ARM. [1] https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi