Commit 07367b8f authored by Simon Glass's avatar Simon Glass
Browse files

cros: x86: Pending updates for samus support

- x86 tweaks
- updates to cros for recent vboot changes

Change-Id: Ida6575aea01acb4852905f6f78631b6af8568bdc
parent f8f978c7
......@@ -1397,6 +1397,7 @@ quiet_cmd_ldr = LD $@
cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
$(filter-out FORCE,$^) -o $@
#BINMAN_u-boot.rom := -i rom
u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin) \
......
......@@ -50,6 +50,10 @@ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-$(CONFIG_APIC) += lapic.o ioapic.o
obj-y += irq.o
ifneq ($(CONFIG_$(SPL_)X86_32BIT_INIT),)
obj-$(CONFIG_SMP) += mp_init.o
endif
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
endif
......
......@@ -11,6 +11,13 @@
#include <asm/arch/pch.h>
#include <asm/arch/pei_data.h>
__weak asmlinkage void sdram_console_tx_byte(unsigned char byte)
{
#ifdef DEBUG
putc(byte);
#endif
}
void broadwell_fill_pei_data(struct pei_data *pei_data)
{
pei_data->pei_version = PEI_VERSION;
......
......@@ -489,10 +489,16 @@ static int broadwell_pch_init(struct udevice *dev)
static int broadwell_pch_probe(struct udevice *dev)
{
if (!(gd->flags & GD_FLG_RELOC))
return broadwell_pch_early_init(dev);
else
if (CONFIG_IS_ENABLED(X86_32BIT_INIT)) {
if (!(gd->flags & GD_FLG_RELOC))
return broadwell_pch_early_init(dev);
else
return broadwell_pch_init(dev);
} else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
return broadwell_pch_init(dev);
} else {
return 0;
}
}
static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
......
......@@ -212,8 +212,10 @@ int last_stage_init(void)
static int x86_init_cpus(void)
{
#ifdef CONFIG_SMP
# if CONFIG_IS_ENABLED(X86_32BIT_INIT) || !defined(CONFIG_X86_RUN_64BIT)
debug("Init additional CPUs\n");
x86_mp_init();
# endif
#else
struct udevice *dev;
......@@ -237,8 +239,9 @@ int cpu_init_r(void)
return 0;
ret = x86_init_cpus();
if (ret)
return ret;
#warning "skip"
// if (ret)
// return ret;
/*
* Set up the northbridge, PCH and LPC if available. Note that these
......
......@@ -190,6 +190,17 @@ board_init_f_r_trampoline:
/* Re-enter U-Boot by calling board_init_f_r() */
call board_init_f_r
.globl jump_to_spl
.type jump_to_spl, @function
jump_to_spl:
/* Reset stack to the top of CAR space */
movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif
jmp *%eax
die:
hlt
jmp die
......
......@@ -8,8 +8,6 @@
#ifndef _COREBOOT_SYSINFO_H
#define _COREBOOT_SYSINFO_H
#include <asm/coreboot_tables.h>
/* Maximum number of memory range definitions */
#define SYSINFO_MAX_MEM_RANGES 32
/* Allow a maximum of 8 GPIOs */
......@@ -57,4 +55,6 @@ extern struct sysinfo_t lib_sysinfo;
int get_coreboot_info(struct sysinfo_t *info);
struct sysinfo_t *lib_sysinfo_get(void);
#endif
......@@ -8,6 +8,8 @@
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
struct memory_area;
struct cbuint64 {
u32 lo;
u32 hi;
......
......@@ -60,6 +60,14 @@ config TARGET_CHROMEBOOK_SAMUS_TPL
between different A/B versions of SPL/U-Boot, to allow upgrading of
almost all U-Boot code in the field.
config TARGET_CHROMEOS_SAMUS
bool "Chromium OS samus"
help
This is a version of Samus which boots Chromium OS verified boot.
See the instructions in doc/README.chromium for more information on
how to build and run this. The Chromium OS interface code is located
in the cros/ subdirectory.
endchoice
source "board/google/chromebook_link/Kconfig"
......
if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL || TARGET_CHROMEOS_SAMUS
config SYS_BOARD
default "chromebook_samus"
......@@ -12,6 +12,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
default "chromeos_samus" if TARGET_CHROMEOS_SAMUS
config SYS_TEXT_BASE
default 0xffe00000
......
......@@ -11,3 +11,10 @@ S: Maintained
F: board/google/chromebook_samus/
F: include/configs/chromebook_samus.h
F: configs/chromebook_samus_tpl_defconfig
CHROMEOS SAMUS BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/chromebook_samus/
F: include/configs/chromeos_samus.h
F: configs/chromeos_samus_defconfig
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0xffed0000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_TARGET_CHROMEOS_SAMUS=y
CONFIG_DEBUG_UART=y
CONFIG_HAVE_MRC=y
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LOG_MAX_LEVEL=6
CONFIG_SPL_LOG_MAX_LEVEL=7
CONFIG_TPL_LOG_MAX_LEVEL=6
CONFIG_LOG_DEFAULT_LEVEL=7
CONFIG_LOG_ERROR_RETURN=y
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0xff7c0000
CONFIG_HANDOFF=y
# CONFIG_SPL_ENV_SUPPORT is not set
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_SPL_RTC_SUPPORT=y
# CONFIG_TPL_ENV_SUPPORT is not set
CONFIG_TPL_PCI=y
CONFIG_TPL_PCH_SUPPORT=y
CONFIG_TPL_RTC_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
# CONFIG_SPL_MAC_PARTITION is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_MISC=y
CONFIG_TPL_MISC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPL_CROS_EC_LPC=y
CONFIG_TPL_CROS_EC_LPC=y
CONFIG_SPL_DM_RTC=y
CONFIG_TPL_DM_RTC=y
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_SOUND=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_CHROMEOS=y
CONFIG_SPL_CHROMEOS=y
# CONFIG_EFI_LOADER is not set
CONFIG_SPL_BOOTSTAGE=y
CONFIG_TPL_BOOTSTAGE=y
CONFIG_SPL_SEPARATE_BSS=y
......@@ -17,7 +17,7 @@
chromeos-config {
u-boot,dm-pre-reloc;
detachable-ui;
/*detachable-ui;*/
recovery-mode-mrc-cache;
/* Kernel start address and size */
......
......@@ -142,7 +142,7 @@ int vboot_ver_init(struct vboot_info *vboot)
if (vboot_flag_read_walk(VBOOT_FLAG_RECOVERY) == 1) {
if (vboot->disable_dev_on_rec)
ctx->flags |= VB2_DISABLE_DEVELOPER_MODE;
ctx->flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE;
}
if (vboot_flag_read_walk(VBOOT_FLAG_WIPEOUT) == 1)
......
......@@ -66,7 +66,8 @@ static void print_on_center(struct udevice *console, const char *message)
out_line(console, '.', cols);
}
VbError_t VbExDisplayScreen(u32 screen_type, u32 locale)
VbError_t VbExDisplayScreen(u32 screen_type, u32 locale,
const VbScreenData *data)
{
struct vboot_info *vboot = vboot_get();
const char *msg = NULL;
......@@ -164,7 +165,7 @@ static void show_cdata_string(struct udevice *console, const char *prompt,
out_str(console, "\n");
}
VbError_t VbExDisplayDebugInfo(const char *info_str)
VbError_t VbExDisplayDebugInfo(const char *info_str, int full_info)
{
struct vboot_info *vboot = vboot_get();
struct udevice *console = vboot->console;
......@@ -179,7 +180,7 @@ VbError_t VbExDisplayDebugInfo(const char *info_str)
return VBERROR_SUCCESS;
}
VbError_t VbExGetlocalisationCount(u32 *count)
VbError_t VbExGetLocalizationCount(u32 *count)
{
*count = vboot_get_locale_count();
......
......@@ -51,7 +51,7 @@ static void fill_handoff(struct vboot_info *vboot,
*oflags |= VB_INIT_OUT_ENABLE_DISPLAY;
*oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE;
}
if (vb2_sd->flags & VB2_SD_DEV_MODE_ENABLED) {
if (vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) {
*oflags |= VB_INIT_OUT_ENABLE_DEVELOPER;
*oflags |= VB_INIT_OUT_CLEAR_RAM;
*oflags |= VB_INIT_OUT_ENABLE_DISPLAY;
......
......@@ -9,7 +9,7 @@
#include <os.h>
#include <cros/vboot.h>
int VbExLegacy(int altfw_num)
int VbExLegacy(enum VbAltFwIndex_t altfw_num)
{
/* TODO(sjg@chromium.org): Implement this */
printf("Legacy boot %d\n", altfw_num);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment