Commit 285edfd7 authored by Michael Walle's avatar Michael Walle Committed by Peng Fan
Browse files

mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()

Since the beginning of this driver which was initially for the MPC8379
and MPC8536 SoCs, there is this spurious 1ms delay. According to the
comment it should actually be only 8 clock cycles. Esp. during EFI block
transfers, this 1ms add up to a significant delay and slows down EFI

I couldn't find any mention in the MPC8536 that there should be a delay
of 8 clock cycles between commands. The SD card specification mentions that
the clock has to be left enabled for 8 cycles after a command or
response. But I don't see how this delay will help with this.

Go ahead and just remove it. If there will ever be any regression we can
introduce a compile time flag, but for now I'd like to keep it simple.

In the split off imx driver this delay was also removed in commit

 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending
Signed-off-by: default avatarMichael Walle <>
parent fb8c2e8f
...@@ -361,13 +361,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, ...@@ -361,13 +361,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA) while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
; ;
/* Wait at least 8 SD clock cycles before the next command */
* Note: This is way more than 8 cycles, but 1ms seems to
* resolve timing issues with some cards
/* Set up for a data transfer if we have one */ /* Set up for a data transfer if we have one */
if (data) { if (data) {
err = esdhc_setup_data(priv, mmc, data); err = esdhc_setup_data(priv, mmc, data);
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