Commit aec4298c authored by Thierry Reding's avatar Thierry Reding Committed by Tom Rini
Browse files

pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS



If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
parent d94d9aa6
...@@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, ...@@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *); struct pci_config_table *);
#define MAX_PCI_REGIONS 7 #ifdef CONFIG_NR_DRAM_BANKS
#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
#else
#define MAX_PCI_REGIONS 7
#endif
#define INDIRECT_TYPE_NO_PCIE_LINK 1 #define INDIRECT_TYPE_NO_PCIE_LINK 1
......
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