This reverts commit f7597730.

This reverts commit 368a0dfb.

This reverts commit c16b137e.

Some libraries build by U-Boot may include stdint.h. This is not used by
U-Boot itself and causes conflicts with the types defined in
linux/types.h. To work around this, add an empty file with this name so
that it will be used in preference to the compiler version.

Change-Id: Ieecb387277c537d30c6521fce9ce9f129a6e053f
Signed-off-by: Simon Glass <sjg@chromium.org>

vb2_nv_regen_crc() is not exported by vboot by default. Drop this code for
now.

Change-Id: I589c375c732139d2a878f2cadb1563e0f28e7415
Signed-off-by: Simon Glass <sjg@chromium.org>

Add the required config and features to make this work. This includes:

- new board called chromeos_sandbox
- new SPL boot method
- make board_run_command() weak

Change-Id: I4ae19f8328dcf72a9b6ef625fcc443a8a52d1125
Signed-off-by: Simon Glass <sjg@chromium.org>

Add Chromium OS's code and vboot library into the build.

Change-Id: I0f741e2ada7d6b76d7917b2209aeb49e43692a0a
Signed-off-by: Simon Glass <sjg@chromium.org>

Add a few hooks and fields which are required by Chromium OS.

Change-Id: Id996434a10c426b04fab48c1a0925677a616a564
Signed-off-by: Simon Glass <sjg@chromium.org>

Add an implementation of Chromium OS verified boot. This is entirely
contained within the cros/ subdrectory. It includes drivers, device-tree
files, commands and callbacks.

Change-Id: Icb4e2eb64116293d5ac1b63db8c771b03ec7bcc6

This includes locale images and developer keys from the Chrome OS repo and
images.

Change-Id: I49f27bba306166516d5ee1d247ca20c52a2f404f
Signed-off-by: Simon Glass <sjg@chromium.org>

As an experiment, build U-Boot as a library, u-boot.o, so it can be used
by other open-source software. Update the sandbox build rules to suit.

This has not been tested in any meaningful way. It breaks sandbox_spl and
all x86 boards.

I am interested in feedback as to how useful this might be.

Signed-off-by: Simon Glass <sjg@chromium.org>
Series-to: u-boot
Cover-letter:
Various patches for verified boot support
This is (for now) the last series to enable Chromium OS verified boot in
U-Boot. It includes:

- Sandbox valgrind spport
- Minor TPM enhancements and fixes
- Resurection of inttypes.h
- Args checking for log functions
- Sandbox fix for time jitter
- Various other minir things
END

It is useful to run sandbox from valgrind to find memory errors, etc. At
present this works OK until U-Boot jumps into the next phase (e.g. from
SPL to U-Boot). Update os_jump_to_file() to use valgrind for each
subsequent phase also.

Signed-off-by: Simon Glass <sjg@chromium.org>

MMC devices support multiple partitions, defined by the hardware. At
present U-Boot can only access partition zero. Add support for selecting
other partitions.

Also add a way to check if a partition is write-protected.

Note: There is existing support for this in the legacy MMC code, but this
is being removed soon.

Series-to: u-boot
Process-logs: sort, uniq
Series-version: 2
Series-changes: 2
- Drop changes previously applied
- Drop patch 'efi_loader: Don't enable in SPL/TPL by default'

Cover-letter:
sandbox: Changes and improvements to support verified boot
This series compiles a number of fixes and improvement sto sandbox,
cros_ec, tpm and a few other pieces. This allows U-Boot to support
Chromium OS verified boot and assist with debugging of this.
END

Change-Id: I44025b99f36aedf749158db6d9edbb187b3c5c35
Signed-off-by: Simon Glass <sjg@chromium.org>

Some TPMs hang on startup without a short delay after getting the lock.
Add a small delay to cope with this.

Series-changes: 2
- Split out from main TPM patch

Change-Id: I81503d0c44b18f2836061ba26667e425ef37faa7
Signed-off-by: Simon Glass <sjg@chromium.org>

At present to output a log message you need something like:

   log(UCLASS_SPI, LOCL_INFO, "message1");
   log(UCLASS_SPI, LOCL_INFO, "message2");

but many files use the same category throughout. Also it is helpful to
shorten the length of log names, providing helpers for common logging
levels. Add some macros so that it is possible to do:

   (top of file, before #includes)
   #define LOG_CATEGORY UCLASS_SPI

   (later in the file)
   log_info("message1");
   log_debug("message2");
   log_err("message3");

Change-Id: Ie8b318419a5a3df0ec01987e0eb2332f4a044566
Signed-off-by: Simon Glass <sjg@chromium.org>

In some cases it is necessary to read the keyboard in early phases of
U-Boot. The cros_ec keyboard is kept in the misc directory. Update the
config to allow this.

Series-changes: 2
- Leave the misc uclass alone since it stops sandbox_spl working

Change-Id: Ie430a83dc32eca0a827ed278524754ba4f11eda0
Signed-off-by: Simon Glass <sjg@chromium.org>

It can confusing when U-Boot SPL hangs for no obvious reason, when it is
unable to load U-Boot. Add a message to indicate the cause.

Change-Id: Ia59edaef6285051850ca28864155706f266e4fee
Signed-off-by: Simon Glass <sjg@chromium.org>

- Add and enable brcmnand driver on a number of relevant platforms.
  Also add and enable LED drivers on more bcm platforms.
- Various ARMv8 fixes/improvements, including extending PSCI
  functionality.
- fs_loader improvments
- Various FIT/SPL improvements
- PCI bugfixes
- Poplar platform ethernet support
- MediaTek MMC improvements
- Android boot improvements

Eugeniu Rosca authored Apr 08, 2019 and Tom Rini committed Apr 24, 2019

Fix below CP warning triggered by the 'iminfo' output in another patch:
WARNING: 'addrress' may be misspelled - perhaps 'address'?

Fixes: 4f1318b2

 ("common: image: minimal android image iminfo support")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

Eugeniu Rosca authored Apr 08, 2019 and Tom Rini committed Apr 24, 2019

According to Android image format [1], kernel image resides at 1 page
offset from the boot image address. Grab the magic number from there
and allow U-Boot to handle LZ4-compressed KNL binaries instead of
hardcoding compression type to IH_COMP_NONE. Other compression types,
if needed, can be added later.

Tested on H3ULCB-KF using the image detailed in [2].

[1] Excerpt from include/android_image.h
    +-----------------+
    | boot header     | 1 page
    +-----------------+
    | kernel          | n pages
    +-----------------+
    | ramdisk         | m pages
    +-----------------+
    | second stage    | o pages
    +-----------------+

[2] => iminfo 4c000000
    ## Checking Image at 4c000000 ...
    Android image found
    kernel size:      85b9d1
    kernel address:   48080000
    ramdisk size:     54ddbc
    ramdisk addrress: 4a180000
    second size:      0
    second address:   48000800
    tags address:     48000100
    page size:        800
    os_version:       1200012a (ver: 0.9.0, level: 2018.10)
    name:
    cmdline:          buildvariant=userdebug

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>

Heinrich Schuchardt authored Apr 07, 2019 and Tom Rini committed Apr 24, 2019

If CONFIG_UNIT_TEST is enabled we should enable the individual tests by
default to ensure good test coverage.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

Lars Povlsen authored Apr 04, 2019 and Tom Rini committed Apr 23, 2019

This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.

When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>

Trent Piepho authored Mar 27, 2019 and Tom Rini committed Apr 23, 2019

The cache flush of the kernel load area needs to be aligned outward to
the DMA cache alignment.  The operations are simpler if we think of this
as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and
aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find
the length of the flushed region by subtracting the former from the
latter.

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Andreas Dannenberg authored Mar 27, 2019 and Tom Rini committed Apr 23, 2019

When using memalign() in a scenario where U-Boot is configured for full
malloc support with simple malloc not explicitly enabled and before the
full malloc support is initialized, a memory block is being allocated
and returned without the alignment parameter getting honored.

Fix this issue by replacing the existing memalign pre-full malloc init
logic with a call to memalign_simple() this way ensuring proper alignment
of the returned memory block.

Fixes: ee038c58

 ("malloc: Use malloc simple before malloc is fully initialized in memalign()")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Stefan Roese authored Mar 26, 2019 and Tom Rini committed Apr 23, 2019

This patch adds a short message to the SPL NAND loader, which displays
the source and destinations addresses including the size of the
loaded image, like this:

U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100)
Trying to boot from NAND
Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000

I find this message quite helpful - hopefully others do so as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
[trini: Redo whitespace]
Signed-off-by: Tom Rini <trini@konsulko.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.

This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.

Signed-off-by: Fabien Parent <fparent@baylibre.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Add config for handling MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>

Fabien Parent authored Mar 24, 2019 and Tom Rini committed Apr 23, 2019

Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>

Shawn Guo authored Mar 20, 2019 and Tom Rini committed Apr 23, 2019

The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed.  With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Shawn Guo authored Mar 20, 2019 and Tom Rini committed Apr 23, 2019

It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Shawn Guo authored Mar 20, 2019 and Tom Rini committed Apr 23, 2019

It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Shawn Guo authored Mar 20, 2019 and Tom Rini committed Apr 23, 2019

Some reset controllers support different polarities for reset operation,
so let's add a polarity field into struct reset_ctl.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Thierry Reding authored Mar 15, 2019 and Tom Rini committed Apr 23, 2019

If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Thierry Reding authored Mar 15, 2019 and Tom Rini committed Apr 23, 2019

Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Adam Ford authored Mar 15, 2019 and Tom Rini committed Apr 23, 2019

With the migration to DM in SPL and the DT support, the
old legacy code is no longer neaded, so this patch removes it

Signed-off-by: Adam Ford <aford173@gmail.com>