Commits · 7ca1af635ac7a323f2715e6478173f3c8eb8c413 · U-Boot / Custodians / Driver Model U-Boot Custodian Tree

11 Sep, 2021 2 commits

arm: dts: k3-am642-evm-u-boot: Add u-boot, dm-spl tag in the pinmux node of mmc1 · 7ca1af63

Aswath Govindraju authored Aug 09, 2021 and

Tom Rini committed Sep 10, 2021

Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.

Fixes: b6059ddc

 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>

7ca1af63

am33xx: Fix USB for am335x boards · 4c9289f5

Matwey V. Kornilov authored Aug 07, 2021 and

Tom Rini committed Sep 10, 2021

USB nodes were mistakenly disabled in

    commit 942853dd ("arm: dts: Resync BeagleBone device trees")

This commit is to fix the following issue:

    starting USB...
    No working controllers found
    USB is stopped. Please issue 'usb start' first.
    starting USB...
    No working controllers found

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85
Fixes: 942853dd

 ("arm: dts: Resync BeagleBone device trees")
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Paul Barker <paul.barker@sancloud.com>

4c9289f5

10 Sep, 2021 1 commit

arm: mvebu: dts: Armada8k enable mdio · 88426bd6

Sven Auhagen authored Aug 24, 2021 and

Stefan Roese committed Sep 10, 2021



Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>

88426bd6

26 Aug, 2021 9 commits

xilinx: common: Enabling generic function for DT reselection · 52ff1626

Michal Simek authored Aug 11, 2021



U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.

When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.

If CC is not present or more are available it keeps going.

When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.

From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.

That's why configuration like:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board", "cc";
};

needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo

and only one dtb is in fit:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board-cc";
};

For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb

When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

52ff1626

arm64: dts: Make sure that all DTBs are 64bit aligned · f28a22d5

Michal Simek authored Aug 19, 2021

Start of DTB should be 64bit aligned that's why also make sure that end is
also 64bit aligned. It is not required but it is nice thing to do.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

f28a22d5

ARM: zynq: Enable smcc and nor for zc770-xm012 · c2b72443

Michal Simek authored Aug 06, 2021



Enable cfi flash on zc770-xm012 configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

c2b72443

ARM: zynq: Wire single qspi on couple of boards · 0df062bf

Michal Simek authored Aug 06, 2021



Single configuration is working fine and no issue to enable it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

0df062bf

ARM: zynq: Replace 'io-standard' with 'power-source' property · b9c4e8d4

Sai Krishna Potthuri authored Aug 06, 2021

Replace 'io-standard' property with 'power-source' property in all
zynq dts files to be in sync with Zynq Pinctrl driver.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

b9c4e8d4

xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP) · bc353102

Raju Kumar Pothuraju authored Jul 01, 2021



Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:

Zynq> sf probe 0 0 0
 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00  Failed to initialize SPI flash at 0:0 (error -2)
Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

bc353102

arm64: zynqmp: Update comment style sm-k26 · 1759a312
Michal Simek authored Aug 05, 2021
```
Trivial style patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
```
1759a312
arm64: zynqmp: Fix header alignment on kv260 boards · 464f6558
Michal Simek authored Aug 06, 2021
```
Fix header alignment.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
```
464f6558

arm64: zynqmp: Fix node name for ds35/36 leds · 4cec057f

Michal Simek authored Aug 06, 2021



By dt-binding specs led nodes should have -led suffix that's why add it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

4cec057f

25 Aug, 2021 1 commit

arm: dts: Add base dtsi and devkit dts for Intel N5X device · 8208e9a9

Siew Chin Lim authored Aug 10, 2021



Add device tree for N5X.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>

8208e9a9

24 Aug, 2021 1 commit

ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash · 221146c5

Adam Ford authored Aug 24, 2021



There is a QSPI NOR flash part on the board.  Because this chip isn't
yet supported in Linux, but it is supported in U-Boot, and the
face that the RPC_SPI compatible names are different in U-Boot and
Linux, the device tree updates are confined to -u-boot.dtsi files.

In order to use the QSPI, TF-A must leave RPC unlocked by compiling
TF-A with RZG_RPC_HYPERFLASH_LOCKED=0.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Biju Bas <biju.das.jz@bp.renesas.com>

221146c5

18 Aug, 2021 1 commit

board: sl28: drop unneeded and outdated flash partitions · 8331618c

Michael Walle authored Jul 26, 2021 and

Priyanka Jain committed Aug 18, 2021



This board doesn't use the MTD subsystem in u-boot, thus there is no
need to specify the partitions. They are outdated anyway. Just drop
them.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

8331618c

16 Aug, 2021 4 commits

ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz · 59f6eb47

Marek Vasut authored Aug 09, 2021 and

Patrice Chotard committed Aug 16, 2021



The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.

There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex for SPL, so opt for the second option. This incurs 20ms delay
during boot, when SPL loads U-Boot to DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

59f6eb47

arm: dts: stm32mp15: alignment with v5.14 · 2d4180b1

Patrick Delaunay authored Jul 27, 2021 and

Patrice Chotard committed Aug 16, 2021



Device tree alignment with Linux kernel v5.14-rc3
- ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
- ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
- ARM: dts: stm32: add a new DCMI pins group on stm32mp15
- ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

2d4180b1

arm: stm32mp: add defconfig for trusted boot with FIP · b73e8bf4

Patrick Delaunay authored Jul 26, 2021 and

Patrice Chotard committed Aug 16, 2021



Add TF-A FIP support for trusted boot on STM32MP15x,
when STM32MP15x_STM32IMAGE is not activated.

With FIP support the SSBL partition is named "fip" and its size is 4MB,
so the ENV partition name in device tree  (for SD card or eMMC)
or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND)
need to be modified.

With FIP the TEE MTD partitions are removed because the OP-TEE binray are
included in the FIP containers.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

b73e8bf4

arm: stm32mp: handle the OP-TEE nodes in DT with FIP support · f91783ed

Patrick Delaunay authored Jul 26, 2021 and

Patrice Chotard committed Aug 16, 2021



With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE
is not activated), the DT nodes needed by OP-TEE are added by OP-TEE
firmware in U-Boot device tree, present in FIP.

These nodes are only required in trusted boot, when TF-A load the file
u-boot.stm32, including the U-Boot device tree with STM32IMAGE header,
in this case OP-TEE can't update the U-Boot device tree.

Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present
in U-Boot device tree only when needed the function
stm32_fdt_disable_optee can be removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

f91783ed

12 Aug, 2021 5 commits

rockchip: px30: add support for SFC for Odroid Go Advance · d70c0cab

Chris Morgan authored Aug 05, 2021 and

Kever Yang committed Aug 12, 2021



The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
and rx lines to 2 for this reason.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

d70c0cab

rockchip: px30: add the serial flash controller · 08b097c3

Chris Morgan authored Aug 05, 2021 and

Kever Yang committed Aug 12, 2021



Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

08b097c3

arm: dts: sync the Rockhip 3368 SoCs from Linux · 10058347

Peter Robinson authored Jul 22, 2021 and

Kever Yang committed Aug 12, 2021



Sync the rk3368 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

10058347

arm: dts: sync the Rockhip 3328 SoCs from Linux · 27e1b5ee

Peter Robinson authored Jul 22, 2021 and

Kever Yang committed Aug 12, 2021



Sync the rk3328 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

27e1b5ee

arm: dts: sync the Rockhip 3399 SoCs from Linux · 822556a9

Peter Robinson authored Jul 22, 2021 and

Kever Yang committed Aug 12, 2021



Sync the rk3399 DTs and associated bits from 5.14-rc1.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Remove the conflict content for vmarc-som)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

822556a9

11 Aug, 2021 6 commits