- 17 Sep, 2021 1 commit
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There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930c ("clk: add support for TI K3 SoC PLL") Signed-off-by:
Dave Gerlach <d-gerlach@ti.com>
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- 25 Aug, 2021 2 commits
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Siew Chin Lim authored
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by:Siew Chin Lim <elly.siew.chin.lim@intel.com>
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Siew Chin Lim authored
Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by:
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- 21 Aug, 2021 1 commit
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The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by:
Adam Ford <aford173@gmail.com> Reviewed-by:
Sean Anderson <sean.anderson@seco.com>
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- 16 Aug, 2021 1 commit
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Add the support of the BSEC clock used by the STM32MP misc driver since the commit 622c956c ("stm32mp: bsec: manage clock when present in device tree") even if this clock is not yet defined in kernel device tree stm32mp151.dtsi. This patch avoids issue for basic boot when this secure clock are not provided by secure world with SCMI. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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- 12 Aug, 2021 1 commit
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Make px30 SFC clock configurable Signed-off-by:
Jon Lin <jon.lin@rock-chips.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com>
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- 27 Jul, 2021 1 commit
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Patrick Delaunay authored
Add the missing SPI clock even if these instances are not available on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K. With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on customer design without the clock driver error: stm32mp1_clk_get_id: clk id 131 not found Reviewed-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
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- 26 Jul, 2021 1 commit
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Michal Simek authored
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
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- 16 Jul, 2021 1 commit
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Patrick Delaunay authored
Add the support of SYSCFG clock used by syscon driver to prepare the clock management of STM32MP_SYSCON_SYSCFG. This clock is already defined in kernel device tree, stm32mp151.dtsi but not yet supported in the syscon driver: syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; }; It is safe to support this clock in U-Boot driver with RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks enable. Signed-off-by:Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by:
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- 15 Jul, 2021 1 commit
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When the default clocks cannot be set, the clock is silently probed and the error is ignored. This is incorrect, since having the clocks at the correct speed may be important for operation of the system. Fix it by checking the return code. Signed-off-by:Simon Glass <sjg@chromium.org>
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- 14 Jul, 2021 1 commit
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Add clock control for PCIe controller on each SoC. Signed-off-by:Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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- 10 Jul, 2021 1 commit
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Add the clocks for the ECSPI controllers. This is ported from Linux v5.13-rc4. Signed-off-by:Frieder Schrempf <frieder.schrempf@kontron.de>
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- 08 Jul, 2021 1 commit
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Setting DM_FLAG_PRE_RELOC for Armada 3720 clock drivers (TBG and peripheral clocks) makes it possible for serial driver to retrieve clock rates via clk API. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Stefan Roese <sr@denx.de>
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- 06 Jul, 2021 2 commits
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Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
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Green Wan authored
Replace 'pciaux' with 'pcieaux', including name string and function prefix. The old name string, 'pciaux', might cause an error if PCIe driver is changed to use clk_get_by_name() with 'pcieaux' to get clock. Signed-off-by:
Green Wan <green.wan@sifive.com> Reviewed-by:
Leo Yu-Chi Liang <ycliang@andestech.com>
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- 24 Jun, 2021 2 commits
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Hai Pham authored
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by:Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
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Marek Vasut authored
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code. Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
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- 23 Jun, 2021 1 commit
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Zhengxun authored
The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by:
Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by:
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- 18 Jun, 2021 2 commits
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Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
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Add rk3568 clock driver and cru structure definition. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by:
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- 17 Jun, 2021 8 commits
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Sean Anderson authored
Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
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Sean Anderson authored
This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by:
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Sean Anderson authored
This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by:
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Sean Anderson authored
This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by:
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Sean Anderson authored
Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by:
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Sean Anderson authored
Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by:
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Sean Anderson authored
This is effectively a complete rewrite to remove all dependency on CCF. The code is now smaller, and so is the binary. It also takes up less memory at runtime (since we don't have to create 40 udevices). In general, I am much happier with this driver as much of the complexity and late binding has been removed. The k210_*_params structs which were previously used to initialize CCF clocks are now used as the complete configuration. Since we can write our own division logic, we can now do away with several "half" clocks which only existed to provide constant factors of two. The clock IDs have been renumbered to remove unused clocks. This may not be the last time they are renumbered, since we have diverged with Linux. There are also still a few clocks left out which may need to be added back in. In general, I have tried to leave out behavioral changes. However, there is a small bugfix regarding ACLK. According to the technical reference manual, its mux comes *after* its divider (which is present only for PLL0). This would have required yet another intermediate clock to fix with CCF, but with the new driver it is just 2 lines of code :) Signed-off-by:
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Sean Anderson authored
Since 291da96b ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by:
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- 11 Jun, 2021 7 commits
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Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
Tero Kristo <kristo@kernel.org>
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Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by:
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Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by:
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If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by:
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Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success. Signed-off-by:
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Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by:
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Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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- 09 Jun, 2021 2 commits
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Usb needs IMXRT1050_CLK_USBOH3 clock to be enabled, so let's add it to clock driver. Signed-off-by:Giulio Benetti <giulio.benetti@benettiengineering.com>
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Lcd peripheral needs 2 different gates to be enable to work, so let's introduce the missing one(LCDIF_PIX) and rename the existing one (LCDIF_APB). Signed-off-by:
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- 31 May, 2021 1 commit
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Green Wan authored
Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by:
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- 24 May, 2021 1 commit
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This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by:
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- 21 May, 2021 1 commit
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Marek Vasut authored
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by:
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