1. 17 Sep, 2021 1 commit
    • Dave Gerlach's avatar
      clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write · d3c56e2a
      Dave Gerlach authored and Tom Rini's avatar Tom Rini committed
      There are three different divider values in the DIV_CTRL register
      controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
      function writes the entire register when programming plld, even though
      plld only resides in the lower 6 bits.
      
      Change the plld programming to read-modify-write to only affect the
      relevant bits for plld and to preserve the other two divider values
      present in the upper 16 bits, otherwise they will always get set to zero
      when programming plld.
      
      Fixes: 0aa2930c
      
       ("clk: add support for TI K3 SoC PLL")
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      d3c56e2a
  2. 25 Aug, 2021 2 commits
  3. 21 Aug, 2021 1 commit
    • Adam Ford's avatar
      clk: clk_versaclock: Add support for versaclock driver · dcf2cee7
      Adam Ford authored and Tom Rini's avatar Tom Rini committed
      
      
      The driver is based on the Versaclock driver from the Linux code, but
      due differences in the clock API between them, some pieces had to be
      changed.
      
      This driver creates a mux, pfd, pll, and a series of fod ouputs.
       Rate               Usecnt      Name
      ------------------------------------------
       25000000             0        `-- x304-clock
       25000000             0            `-- clock-controller@6a.mux
       25000000             0                |-- clock-controller@6a.pfd
       2800000000           0                |   `-- clock-controller@6a.pll
       33333333             0                |       |-- clock-controller@6a.fod0
       33333333             0                |       |   `-- clock-controller@6a.out1
       33333333             0                |       |-- clock-controller@6a.fod1
       33333333             0                |       |   `-- clock-controller@6a.out2
       50000000             0                |       |-- clock-controller@6a.fod2
       50000000             0                |       |   `-- clock-controller@6a.out3
       125000000            0                |       `-- clock-controller@6a.fod3
       125000000            0                |           `-- clock-controller@6a.out4
       25000000             0                `-- clock-controller@6a.out0_sel_i2cb
      
      A translation function is added so the references to <&versaclock X> get routed
      to the corresponding clock-controller@6a.outX.
      Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
      Reviewed-by: default avatarSean Anderson <sean.anderson@seco.com>
      dcf2cee7
  4. 16 Aug, 2021 1 commit
  5. 12 Aug, 2021 1 commit
  6. 27 Jul, 2021 1 commit
  7. 26 Jul, 2021 1 commit
  8. 16 Jul, 2021 1 commit
  9. 15 Jul, 2021 1 commit
    • Simon Glass's avatar
      clk: Detect failure to set defaults · 92f1e9a4
      Simon Glass authored and Tom Rini's avatar Tom Rini committed
      
      
      When the default clocks cannot be set, the clock is silently probed and
      the error is ignored. This is incorrect, since having the clocks at the
      correct speed may be important for operation of the system.
      
      Fix it by checking the return code.
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      92f1e9a4
  10. 14 Jul, 2021 1 commit
  11. 10 Jul, 2021 1 commit
  12. 08 Jul, 2021 1 commit
  13. 06 Jul, 2021 2 commits
  14. 24 Jun, 2021 2 commits
  15. 23 Jun, 2021 1 commit
  16. 18 Jun, 2021 2 commits
  17. 17 Jun, 2021 8 commits
  18. 11 Jun, 2021 7 commits
  19. 09 Jun, 2021 2 commits
  20. 31 May, 2021 1 commit
  21. 24 May, 2021 1 commit
  22. 21 May, 2021 1 commit