1. 19 Sep, 2021 5 commits
    • Simon Glass's avatar
      doc: test: Explain how to run pytests in parallel · 9666220d
      Simon Glass authored
      
      
      Add documentation for this so people can try it out. At present it does
      not fully work.
      
      Series-to: u-boot
      Series-cc: heinrich, stephen, trini
      Series-links: 254822
      Series-prefix: RESEND
      Series-version: 2
      Series-changes: 2
      - Add documentation for how to run parallel tests
      
      Cover-letter:
      test: Try to deal with some co-dependent tests
      Tests are supposed to be independent. With driver model tests, the
      environment is reset before each test, which ensures that.
      
      With Python tests there is no reset of the board between tests, since we
      want to run all the tests as quickly as possible and without needing the
      external scripts running constantly.
      
      In principle the Python tests can be independent if they each put the
      world back the way they found it, but it turns out that some are not.
      This means that some tests cannot be run unless another test is run
      first. It also means that tests cannot be run in parallel, e.g. on
      sandbox.
      
      This series fixes some of them. Those that remain:
      
         test_gpt_swap_partitions - not sure?
         test_pinmux_status - not sure?
         test_sqfs_load - cannot be run more than once!
         test_bind_unbind_with_uclass - relies on previous test
      
      The last one would be much better done as a C test, so it doesn't have
      to deal with the changing driver tree. There isn't a lot of value in
      running the test on a real board, since sandbox should find any bugs
      in driver model or the 'bind' command.
      
      If the above can be resolved we can enable parallel tests. On my test
      machine (32 threads) it reduces the time from 38 seconds to 7.5s
      
      To use this feature, see the documentaiton added, or:
      
         pip3 install pytest-xdist
      
         test/py/test.py -B sandbox --build-dir /tmp/xx -q -k 'not slow' -n32
      END
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      Change-Id: I4b868f615036d4b8bc4d9f6a8555db49be9f6009
      9666220d
    • Simon Glass's avatar
      test: Allow tpm2 tests to run in parallel · 6b908422
      Simon Glass authored
      
      
      These tests currently run in a particular sequence, with some of them
      depending on the actions of earlier tests.
      
      Add a check for sandbox and reset to a known state at the start of each
      test, so that all tests can run in parallel.
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      6b908422
    • Simon Glass's avatar
      test: Allow hush tests to run in parallel · 9b7b140c
      Simon Glass authored
      
      
      The -z tests don't really need to be part of the main set. Separate them
      out so we can drop the test setup/cleans functions and thus run all tests
      in parallel.
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      9b7b140c
    • Simon Glass's avatar
      test: Allow vboot tests to run in parallel · bf170ef9
      Simon Glass authored
      
      
      Update the tests to use separate working directories, so we can run them
      in parallel. It also makes it possible to see the individual output files
      after the tests have completed.
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      bf170ef9
    • Tom Rini's avatar
      Merge tag 'dm-pull-18sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm · 3f571228
      Tom Rini authored
      Revert the public-key-embedded-in-executable patches so this does not form
      part of an official release before it is agreed.
      3f571228
  2. 18 Sep, 2021 3 commits
  3. 17 Sep, 2021 11 commits
    • Tom Rini's avatar
      Merge branch '2021-09-17-TI-platform-updates' · d0b8c9a2
      Tom Rini authored
      - Assorted bugfixes for TI platforms
      d0b8c9a2
    • Nishanth Menon's avatar
      arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup · ee91d465
      Nishanth Menon authored and Tom Rini's avatar Tom Rini committed
      
      
      With Device Manager firmware in an elf file form, we cannot load the FIT
      image to the exact same address as any of the executable sections of the
      elf file itself is located.
      
      However, the device tree descriptions for the ARMV8 bootloader/OS
      includes DDR regions only the final sections in DDR where the Device
      Manager firmware is actually executing out of.
      
      As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
      by starting the Armv8 ahead of parsing the elf and copying the correct
      sections to the required memories creates a race condition where the
      ARMv8 could overwrite the elf image loaded from the FIT image prior to
      the R5 completing parsing and putting the correct sections of elf in
      the required memory locations. OR create rather obscure debug conditions
      where data in the section is being modified by ARMV8 OS while the elf
      copy is in progress.
      
      To prevent all these conditions, lets make sure that the elf parse and
      copy operations are completed ahead of ARMv8 being released to execute.
      
      We will pay a penalty of elf copy time, but that is a valid tradeoff in
      comparison to debug of alternate scenarios.
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      ee91d465
    • Roger Quadros's avatar
      arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge · 6887f8e0
      Roger Quadros authored and Tom Rini's avatar Tom Rini committed
      
      
      NB0 is bridge to SRAM and NB1 is bridge to DDR.
      
      To ensure that SRAM transfers are not stalled due to delays during DDR
      refreshes, SRAM traffic should be higher priority (threadmap=2) than
      DDR traffic (threadmap=0).
      
      This fixup is critical to provide deterministic access latency to
      MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
      to incorrect reset values (has no erratum id) and statically setting
      things up should be done independent of usecases and board.
      
      This specific style of Northbridge configuration is specific only to
      AM65x devices, follow-on K3 devices have different data prioritization
      schemes (ASEL and the like) and hence the fixup applies purely to
      AM65x.
      
      Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
      case of SR1 devices, on SR2 devices, lockups were not observed so far
      but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
      throughput.
      Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
      Acked-by: default avatarAndrew F. Davis <afd@ti.com>
      Acked-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Acked-by: default avatarBenoit Parrot <bparrot@ti.com>
      [Jan: rebased, dropped used define, extended commit log]
      Signed-off-by: Jan Kiszka's avatarJan Kiszka <jan.kiszka@siemens.com>
      [Nishanth: Provide relevant context in the commit message]
      Signed-off-by: Nishanth Menon<nm@ti.com>
      6887f8e0
    • Suman Anna's avatar
      clk: ti: k3: Update driver to account for divider flags · cfd50dfb
      Suman Anna authored and Tom Rini's avatar Tom Rini committed
      
      
      The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
      turn serve as inputs to other HSDIV output clocks. These clocks use
      the actual value to compute the divider clock rate, and need to be
      registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
      driver and data lacks the infrastructure to pass in divider flags.
      Update the driver and data to account for these divider flags.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      cfd50dfb
    • Dave Gerlach's avatar
      clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write · d3c56e2a
      Dave Gerlach authored and Tom Rini's avatar Tom Rini committed
      There are three different divider values in the DIV_CTRL register
      controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
      function writes the entire register when programming plld, even though
      plld only resides in the lower 6 bits.
      
      Change the plld programming to read-modify-write to only affect the
      relevant bits for plld and to preserve the other two divider values
      present in the upper 16 bits, otherwise they will always get set to zero
      when programming plld.
      
      Fixes: 0aa2930c
      
       ("clk: add support for TI K3 SoC PLL")
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      d3c56e2a
    • Dave Gerlach's avatar
      arm: mach-k3: Add note to auto-generated files · ae8d3d23
      Dave Gerlach authored and Tom Rini's avatar Tom Rini committed
      
      
      Add a note to the automatically generated clk-data and dev-data files
      for j721e and j7200 to indicate that they are in fact auto-generated and
      should not be hand edited.
      
      Also adjust TI URL to use https instead of http and also add an empty
      line before first header inclusion.
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      ae8d3d23
    • Suman Anna's avatar
      arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks · 326c03b5
      Suman Anna authored and Tom Rini's avatar Tom Rini committed
      The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
      divisors to generate the final FOUTPOSTDIV clock. These are in sequence
      with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
      has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
      opposite of the actual implementation. Fix the data by simply adjusting
      the register bit-shifts.
      
      The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
      register values, fix these as well.
      
      Fixes: 277729ea
      
       ("arm: mach-k3: Add platform data for j721e and j7200")
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      326c03b5
    • Suman Anna's avatar
      arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks · f1a815d0
      Suman Anna authored and Tom Rini's avatar Tom Rini committed
      The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
      divisors to generate the final FOUTPOSTDIV clock. These are in sequence
      with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
      has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
      opposite of the actual implementation. Fix the data by simply adjusting
      the register bit-shifts.
      
      The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
      register values, fix these as well.
      
      Fixes: 277729ea
      
       ("arm: mach-k3: Add platform data for j721e and j7200")
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      f1a815d0
    • Suman Anna's avatar
      arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub · d86a089d
      Suman Anna authored and Tom Rini's avatar Tom Rini committed
      
      
      Add a weak release_resources_for_core_shutdown() stub implementation
      that can be overridden by actual implementation if a SoC supports that
      function.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Reviewed-by: default avatarNishanth Menon <nm@ti.com>
      d86a089d
    • Suman Anna's avatar
      firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h · 04662755
      Suman Anna authored and Tom Rini's avatar Tom Rini committed
      
      
      The common TI SCI header file uses some macros from err.h and these
      get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
      the linux/err.h header file in this header file directly rather
      than relying on source files to include it to eliminate any
      potential build errors.
      
      While at this, reorder the existing header file include to the
      beginning of the file.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Reviewed-by: default avatarNishanth Menon <nm@ti.com>
      04662755
    • Christophe Leroy's avatar
      MAINTAINERS: POWERPC MPC8XX: Update email address · 12ff1a8d
      Christophe Leroy authored and Tom Rini's avatar Tom Rini committed
      
      
      Our email addresses have changed from @c-s.fr to @csgroup.eu
      
      Update entry in MAINTAINERS
      Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
      12ff1a8d
  4. 15 Sep, 2021 5 commits
  5. 14 Sep, 2021 9 commits
  6. 13 Sep, 2021 7 commits