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  • Grzegorz Jaszczyk's avatar
    phy: marvell: fix pll initialization for second utmi port · a007f236
    Grzegorz Jaszczyk authored and Stefan Roese's avatar Stefan Roese committed
    
    
    According to Design Reference Specification the PHY PLL and Calibration
    register from PHY0 are shared for multi-port PHY. PLL control registers
    inside other PHY channels are not used.
    
    This commit reworks utmi device tree nodes in a way that common PHY PLL
    registers are moved to main utmi node. Accordingly both child nodes
    utmi-unit range is reduced and register offsets in utmi_phy.h are updated
    to this change.
    
    This fixes issues in scenarios when only utmi port1 was in use, which
    resulted with lack of correct pll initialization.
    
    Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097
    Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
    a007f236