Commit 1c02fd46 authored by Tom Rini's avatar Tom Rini
Browse files
parents ad320c23 30fa33dc
......@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config SIFIVE_CACHE
bool
help
This enables the operations to configure SiFive cache
config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
......
......@@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
......
......@@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu540-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}
......@@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII
......
......@@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020-2021 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/global_data.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu740-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020-2021 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */
......@@ -8,7 +8,7 @@
#define _ASM_RISCV_CACHE_H
/* cache */
void cache_flush(void);
void cache_flush(void);
/*
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
......
......@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
......
......@@ -70,3 +70,7 @@ __weak int dcache_status(void)
{
return 0;
}
__weak void enable_caches(void)
{
}
......@@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs)
#endif
}
/**
* instr_len() - get instruction length
*
* @i: low 16 bits of the instruction
* Return: number of u16 in instruction
*/
static int instr_len(u16 i)
{
if ((i & 0x03) != 0x03)
return 1;
/* Instructions with more than 32 bits are not yet specified */
return 2;
}
/**
* show_code() - display code leading to exception
*
* @epc: program counter
*/
static void show_code(ulong epc)
{
u16 *pos = (u16 *)(epc & ~1UL);
int i, len = instr_len(*pos);
printf("\nCode: ");
for (i = -8; i; ++i)
printf("%04x ", pos[i]);
printf("(");
for (i = 0; i < len; ++i)
printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " ");
}
static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
{
static const char * const exception_code[] = {
......@@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
epc - gd->reloc_off, regs->ra - gd->reloc_off);
show_regs(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
}
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 SiFive, Inc
*/
#include <common.h>
#include <cache.h>
#include <cpu_func.h>
#include <dm.h>
void enable_caches(void)
{
struct udevice *dev;
int ret;
/* Enable ways of ccache */
ret = uclass_get_device_by_driver(UCLASS_CACHE,
DM_DRIVER_GET(sifive_ccache),
&dev);
if (ret) {
log_debug("Cannot enable cache ways");
} else {
ret = cache_enable(dev);
if (ret)
log_debug("ccache enable failed");
}
}
......@@ -6,6 +6,7 @@
* Anup Patel <anup.patel@wdc.com>
*/
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
......@@ -15,7 +16,6 @@
#include <linux/delay.h>
#include <misc.h>
#include <spl.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
/*
......@@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}
......@@ -7,8 +7,8 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
void *board_fdt_blob_setup(void)
......@@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}
......@@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0;
}
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
/*
* Some of these functions are needed purely because the functions they
* call return void. If we change them to return 0, these stubs can go away.
......@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed,
......
......@@ -10,6 +10,7 @@ CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
......
......@@ -11,6 +11,7 @@ CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
......
......@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
......@@ -28,12 +29,16 @@ CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_DM_RESET=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
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