Commit 213ed175 authored by Zong Li's avatar Zong Li Committed by Leo Yu-Chi Liang
Browse files

riscv: lib: implement enable_caches for sifive cache



The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
parent 4d4222d0
......@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config SIFIVE_CACHE
bool
help
This enables the operations to configure SiFive cache
config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
......
......@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 SiFive, Inc
*/
#include <common.h>
#include <cache.h>
#include <cpu_func.h>
#include <dm.h>
void enable_caches(void)
{
struct udevice *dev;
int ret;
/* Enable ways of ccache */
ret = uclass_get_device_by_driver(UCLASS_CACHE,
DM_DRIVER_GET(sifive_ccache),
&dev);
if (ret) {
log_debug("Cannot enable cache ways");
} else {
ret = cache_enable(dev);
if (ret)
log_debug("ccache enable failed");
}
}
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