Commit 4d4222d0 authored by Zong Li's avatar Zong Li Committed by Leo Yu-Chi Liang
Browse files

common: board_r: support enable_caches for RISC-V



The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
parent 43a21839
......@@ -70,3 +70,7 @@ __weak int dcache_status(void)
{
return 0;
}
__weak void enable_caches(void)
{
}
......@@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0;
}
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
/*
* Some of these functions are needed purely because the functions they
* call return void. If we change them to return 0, these stubs can go away.
......@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed,
......
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