1. 25 Nov, 2013 1 commit
    • Tom Rini's avatar
      hash.c: Correct non-hash subcommand crc32 addr-save support · 4b756b01
      Tom Rini authored
      In the case of not having CONFIG_CMD_HASH but having CONFIG_CMD_CRC32
      enabled (and not CONFIG_CRC32_VERIFY), we end up in this part of the
      code path on hash_command().  However, we will only have exactly 3 args
      here, and 3 > 3 is false, and we will not try and store the hash at the
      address given as arg #3
      
      .  The next problem however is that we've been
      moving argv around so the third value is now in argv[0] not argv[3].
      
      Confirmed on AM335x Beaglebone White.
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      4b756b01
  2. 17 Nov, 2013 24 commits
  3. 15 Nov, 2013 7 commits
  4. 14 Nov, 2013 1 commit
  5. 13 Nov, 2013 7 commits
    • Laurentiu TUDOR's avatar
      powerpc/85xx: fix broken cpu "clock-frequency" property · 51abee64
      Laurentiu TUDOR authored
      
      
      When indexing freqProcessor[] we use the first
      value in the cpu's "reg" property, which on
      new e6500 cores IDs the threads.
      But freqProcessor[] should be indexed with a
      core index so, when fixing "the clock-frequency"
      cpu node property, access the freqProcessor[]
      with the core index derived from the "reg' property.
      If we don't do this, last half of the "cpu" nodes
      will have broken "clock-frequency" values.
      Signed-off-by: default avatarLaurentiu Tudor <Laurentiu.Tudor@freescale.com>
      Cc: York Sun <yorksun@freescale.com>
      51abee64
    • Laurentiu TUDOR's avatar
      powerpc/t4240: fix per pci endpoint liodn offsets · 8f9fe660
      Laurentiu TUDOR authored
      
      
      Update the code that builds the pci endpoint liodn
      offset list so that it doesn't overlap with other
      liodns and doesn't generate negative offsets like:
      
        fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                                   0xffffffd1 0xffffffd3
                                   0xffffffd5 0xffffffd7
                                   0xffffffd9 0xffffffdb>;
      
      The update consists in adding a parameter to the
      function that builds the list to specify the base
      liodn.
      On PCI v2.4 use the old base = 256 and, on PCI 3.0
      where some of the PCIE liodns are larger than 256,
      use a base = 1024. The version check is based on
      the PCI controller's version register.
      Signed-off-by: default avatarLaurentiu Tudor <Laurentiu.Tudor@freescale.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: York Sun <yorksun@freescale.com>
      8f9fe660
    • Laurentiu TUDOR's avatar
      powerpc/t4240: set pcie liodn in the correct register · b4125a23
      Laurentiu TUDOR authored
      
      
      The liodn for the T4240's PCIE controller is no longer set
      through a register in the guts register block but with one
      in the PCIE register block itself.
      Use the already existing SET_PCI_LIODN_BASE macro that puts
      the liodn in the correct register.
      Signed-off-by: default avatarLaurentiu Tudor <Laurentiu.Tudor@freescale.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: York Sun <yorksun@freescale.com>
      b4125a23
    • ramneek mehresh's avatar
      powerpc/83xx: Define USB1 and USB2 base addr for MPC834x · 4e2e0df9
      ramneek mehresh authored
      
      
      Define base addresse for both MPH(USB1) and DR(USB2) controllers
      for MPC834x socs
      Signed-off-by: default avatarRamneek Mehresh <ramneek.mehresh@freescale.com>
      4e2e0df9
    • Priyanka Jain's avatar
      powerpc/t104xrdb: Add T1042RDB_PI board support · 0d7ba2ea
      Priyanka Jain authored
      
      
      T1042RDB_PI is Freescale Reference Design Board supporting the T1042
      QorIQ Power Architecture™ processor. T1042 is a reduced personality
      of T1040 SoC without Integrated 8-port Gigabit. The board is designed
      with low power features targeted for Printing Image Market.
      
      T1042RDB_PI is  similar to T1040RDB board with few differences like
      it has video interface, supports T1042 personality
      
       T1042RDB_PI board Overview
       -----------------------
       - Four e5500 cores, each with a private 256 KB L2 cache
       - 256 KB shared L3 CoreNet platform cache (CPC)
       - Interconnect CoreNet platform
       - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
         support
       - Data Path Acceleration Architecture (DPAA) incorporating acceleration
       for the following functions:
          -  Packet parsing, classification, and distribution
          -  Queue management for scheduling, packet sequencing, and congestion
          	management
          -  Cryptography Acceleration
          - RegEx Pattern Matching Acceleration
          - IEEE Std 1588 support
          - Hardware buffer management for buffer allocation and deallocation
       - Ethernet interfaces
          - Two on-board RGMII 10/100/1G ethernet ports.
       - SERDES Connections, 8 lanes supporting:
            — PCI
            — SATA 2.0
       - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
         Interleaving
       -IFC/Local Bus
           - NAND flash: 1GB 8-bit NAND flash
           - NOR: 128MB 16-bit NOR Flash
       - Ethernet
           - Two on-board RGMII 10/100/1G ethernet ports.
           - PHY #0 remains powered up during deep-sleep
       - CPLD
       - Clocks
           - System and DDR clock (SYSCLK, “DDRCLK”)
           - SERDES clocks
       - Video
           - DIU supports video at up to 1280x1024x32bpp
           - HDMI connector
       - Power Supplies
       - USB
           - Supports two USB 2.0 ports with integrated PHYs
           - Two type A ports with 5V@1.5A per port.
       - SDHC
           - SDHC/SDXC connector
       - SPI
           - On-board 64MB SPI flash
       - I2C
           - Device connected: EEPROM, thermal monitor, VID controller, RTC
       - Other IO
          - Two Serial ports
          - ProfiBus port
          - Four I2C ports
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      0d7ba2ea
    • Priyanka Jain's avatar
      powerpc/t104xrdb: Add T1040RDB board support · 062ef1a6
      Priyanka Jain authored
      
      
      T1040RDB is Freescale Reference Design Board supporting
      the T1040 QorIQ Power Architecture™ processor.
      
       T1040RDB board Overview
       -----------------------
       - Four e5500 cores, each with a private 256 KB L2 cache
       - 256 KB shared L3 CoreNet platform cache (CPC)
       - Interconnect CoreNet platform
       - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
         support
       - Data Path Acceleration Architecture (DPAA) incorporating acceleration
       for the following functions:
          -  Packet parsing, classification, and distribution
          -  Queue management for scheduling, packet sequencing, and congestion
             management
          -  Cryptography Acceleration
          - RegEx Pattern Matching Acceleration
          - IEEE Std 1588 support
          - Hardware buffer management for buffer allocation and deallocation
       - Ethernet interfaces
          - Integrated 8-port Gigabit Ethernet switch
          - Four 1 Gbps Ethernet controllers
       - SERDES Connections, 8 lanes supporting:
          - PCI
          - SGMII
          - QSGMII
          - SATA 2.0
       - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
         Interleaving
       -IFC/Local Bus
          - NAND flash: 1GB 8-bit NAND flash
          - NOR: 128MB 16-bit NOR Flash
       - Ethernet
          - Two on-board RGMII 10/100/1G ethernet ports.
          - PHY #0 remains powered up during deep-sleep
       - CPLD
       - Clocks
          - System and DDR clock (SYSCLK, “DDRCLK”)
          - SERDES clocks
       - Power Supplies
       - USB
          - Supports two USB 2.0 ports with integrated PHYs
          - Two type A ports with 5V@1.5A per port.
       - SDHC
          - SDHC/SDXC connector
       - SPI
          - On-board 64MB SPI flash
       - I2C
          - Devices connected: EEPROM, thermal monitor, VID controller
       - Other IO
          - Two Serial ports
          - ProfiBus port
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      [York Sun: fixed Makefile]
      Acked-by: default avatarYork Sun <yorksun@freescale.com>
      062ef1a6
    • Priyanka Jain's avatar
      powerpc/t1040: Update defines to support T1040SoC personalities · 2967af68
      Priyanka Jain authored
      
      
      T1040 Soc has four personalities:
      -T1040 (4 cores with L2 switch)
      -T1042:Reduced personality of T1040 without L2 switch
      -T1020:Reduced personality of T1040 with less cores(2 cores)
      -T1022:Reduced personality of T1040 with 2 cores and without L2 switch
      
      Update defines in arch/powerpc header files, Makefiles and in
      driver/net/fm/Makefile to support all T1040 personalities
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      [York Sun: fixed Makefiles]
      Acked-by: default avatarYork Sun <yorksun@freescale.com>
      2967af68