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Improve the IRQ response latency by setting GIC root clock source to sys_pll2_200m from osc. Signed-off-by: Peng Fan <peng.fan@nxp.com>
eeca15a5
Improve the IRQ response latency by setting GIC root clock source to
sys_pll2_200m from osc.
Signed-off-by: Peng Fan <peng.fan@nxp.com>