Commit c04ac5bd authored by Hannes Schmelzer's avatar Hannes Schmelzer Committed by Stefano Babic
Browse files

board/BuR/brppt2: initial commit



This commit adds support for the brppt2 board. The board is based on the
i.mx6 dual-lite SoC.
Signed-off-by: default avatarHannes Schmelzer <hannes.schmelzer@br-automation.com>
parent 910b2fca
......@@ -565,6 +565,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \
imx6dl-brppt2.dtb \
imx6dl-dhcom-pdk2.dtb \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 B&R Industrial Automation GmbH
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-u-boot.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <include/dt-bindings/gpio/gpio.h>
/ {
model = "PPT50";
compatible = "fsl,imx6dl";
config {
u-boot,spl-payload-offset = <0x100000>;
};
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
order-no = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
serial-no = <0>;
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x0>;
};
aliases {
ds1timing0 = &timing0;
ds1timing1 = &timing1;
ds1bkl = &backlight;
fset = &fset;
mxcfb0 = &mxcfb0;
touch0 = &touch0;
touch1 = &touch1;
touch2 = &touch2;
display_regulator = &display_regulator;
ldb = &ldb;
mmc0 = &usdhc4;
};
chosen {
stdout-path = "serial0:115200n8";
};
mxcfb0: fb@0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB24";
default_bpp = <32>;
int_clk = <0>;
late_init = <0>;
rotation = <0>;
status = "okay";
};
lcd@0 {
compatible = "fsl,lcd";
vlcd-supply = <&display_regulator>;
ipu_id = <0>;
disp_id = <0>;
default_ifmt = "RGB24";
status = "disabled";
display-timings {
native-mode = <&timing1>;
timing1: lcd {
};
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100>;
default-brightness-level = <0>;
status = "okay";
enable-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm3 0 0 0>;
};
vbus1_regulator: regulator@1 {
u-boot,dm-preloc;
compatible = "regulator-fixed";
regulator-name = "vbus1_regulator";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vbus2_regulator: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "vbus2_regulator";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usbhub_regulator: gpio-regulator@3 {
compatible = "regulator-gpio";
regulator-name = "ushbub_regulator";
enable-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
enable-at-boot;
states = <0 0 1 1>;
};
display_regulator: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "display_regulator";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <1000>;
};
};
&fec {
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&uart1 {
u-boot,dm-spl;
u-boot,dm-preloc;
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&ldb {
status = "disabled";
vldb-supply = <&display_regulator>;
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "okay";
crtc = "ipu1-di0";
display-timings {
native-mode = <&timing0>;
timing0: lcd {
};
};
};
};
&usdhc4 {
non-removable;
bus-width = <8>;
status = "okay";
};
&usbotg {
vbus-supply = <&vbus1_regulator>;
dr_mode = "host";
status = "okay";
};
&usbh1 {
vbus-supply = <&vbus2_regulator>;
dr_mode = "host";
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
touch0: egalax_i2c@2a {
compatible = "eeti,egalax_i2c";
reg = <0x2a>;
interrupt-parent = <&gpio4>;
interrupts = <9 2>;
int-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
};
touch1: gt911@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio4>;
interrupts = <9 2>;
irq-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
touch2: i2c-hid-dev@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x0001>;
interrupt-parent = <&gpio4>;
interrupts = <9 2>;
status = "disabled";
};
};
&gpio1 {
u-boot,dm-spl;
status = "okay";
};
&gpio2 {
u-boot,dm-spl;
status = "okay";
};
&gpio3 {
u-boot,dm-spl;
status = "okay";
};
&gpio4 {
u-boot,dm-spl;
status = "okay";
};
&usdhc4 {
status = "okay";
};
&ecspi1 {
u-boot,dm-spl;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
spi-max-frequency = <25000000>;
m25p32@1 {
u-boot,dm-spl;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p", "jedec,spi-nor";
spi-max-frequency = <25000000>;
reg = <1>;
};
};
......@@ -596,6 +596,24 @@ config TARGET_ZC5601
select SUPPORT_SPL
imply CMD_DM
config TARGET_BRPPT2
bool "brppt2"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select SUPPORT_SPL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
help
Support
B&R BRPPT2 platform
based on Freescale's iMX6 SoC
endchoice
config SYS_SOC
......@@ -653,5 +671,6 @@ source "board/udoo/Kconfig"
source "board/udoo/neo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
endif
if TARGET_BRPPT2
config SYS_BOARD
default "brppt2"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "brppt2"
config SPL_DM_SPI
def_bool y
endif
BUR_PPT2 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brppt2/
F: include/configs/brppt2.h
F: configs/brppt2_defconfig
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2019
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
obj-y := ../common/common.o
obj-y += board.o
// SPDX-License-Identifier: GPL-2.0+
/*
* Board functions for BuR BRPPT2 board
*
* Copyright (C) 2019
* B&R Industrial Automation GmbH - http://www.br-automation.com/
*
*/
#include <common.h>
#include <spl.h>
#include <dm.h>
#include <miiphy.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#ifdef CONFIG_SPL_BUILD
# include <asm/arch/mx6-ddr.h>
#endif
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define USBHUB_RSTN IMX_GPIO_NR(1, 16)
#define BKLT_EN IMX_GPIO_NR(1, 15)
#define CAPT_INT IMX_GPIO_NR(4, 9)
#define CAPT_RESETN IMX_GPIO_NR(4, 11)
#define SW_INTN IMX_GPIO_NR(3, 26)
#define VCCDISP_EN IMX_GPIO_NR(5, 18)
#define EMMC_RSTN IMX_GPIO_NR(6, 8)
#define PMIC_IRQN IMX_GPIO_NR(5, 22)
#define TASTER IMX_GPIO_NR(5, 23)
#define ETH0_LINK IMX_GPIO_NR(1, 27)
#define ETH1_LINK IMX_GPIO_NR(1, 28)
#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
PAD_CTL_SRE_FAST)
#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
#if !defined(CONFIG_SPL_BUILD)
static iomux_v3_cfg_t const eth_pads[] = {
/*
* Gigabit Ethernet
*/
/* CLKs */
MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
/* MDIO */
MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
/* RGMII */
MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
/* ETH0_LINK */
MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
/* ETH1_LINK */
MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
};
static iomux_v3_cfg_t const board_pads[] = {
/*
* I2C #3, #4
*/
MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
/*
* UART#4 PADS
* UART_Tasten
*/
MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
/*
* ESCPI#1
* M25P32 NOR-Flash
*/
MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
/*
* ESCPI#2
* resTouch SPI ADC
*/
MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
/*
* USDHC#4
*/
MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
/*
* USB OTG power & ID
*/
/* USB_OTG_5V_EN */
MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
/* USB_OTG_JUMPER */
MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
/*
* PWM-Pins
*/
/* BKLT_CTL */
MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
/* SPEAKER */
MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
/*
* GPIOs
*/
/* USB_HUB_nRESET */
MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
/* BKLT_EN */
MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
/* capTouch_INT */
MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
/* capTouch_nRESET */
MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
/* SW_nINT */
MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
/* VCC_DISP_EN */
MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
/* eMMC_nRESET */
MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
/* HWID*/
MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
/* PMIC_nIRQ */
MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
/* nTASTER */
MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
/* RGB LCD Display */
MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
};
int board_ehci_hcd_init(int port)
{
gpio_direction_output(USBHUB_RSTN, 1);
return 0;
}
int board_late_init(void)
{
ulong b_mode = 4;
if (gpio_get_value(TASTER) == 0)
b_mode = 12;
env_set_ulong("b_mode", b_mode);
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
if (gpio_request(BKLT_EN, "BKLT_EN"))
printf("Warning: BKLT_EN setup failed\n");
gpio_direction_output(BKLT_EN, 0);
if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
printf("Warning: USBHUB_nRST setup failed\n");
gpio_direction_output(USBHUB_RSTN, 0);
if (gpio_request(TASTER, "TASTER"))
printf("Warning: TASTER setup failed\n");
gpio_direction_input(TASTER);
return 0;
}
int board_early_init_f(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
SETUP_IOMUX_PADS(board_pads);
SETUP_IOMUX_PADS(eth_pads);